Pipelined ADC enhancement techniques

In this work three techniques to improve pipelined ADC performance with respect to linearity and power consumption are presented. The first technique enables rapid background digital correction of both DAC and gain errors in the multi-bit first stage of an 11-bit pipelined ADC. The proposed rapid calibration scheme enables significantly shorter automated test times in an industrial production environment, hence facilitates larger production throughput and thus increased cost efficiency. Measured results from a prototype fabricated in 1.8V 0.18microm CMOS show the technique achieves an improvement in linearity by more than 20dB within only 104 clock cycles in an 11-bit 45MS/s pipelined ADC---more than two orders of magnitude faster than previously published reports. The second technique develops a new MDAC topology which enables a pipelined ADC to be designed without a front-end sample-and-hold, and thus allows for significant power reduction. Unlike previous reports, the proposed topology does not require a carefully matched and/or time consuming layout to work properly. Measured results from a prototype fabricated in 1.8V 0.18microm CMOS show that better than 51dB SNDR can be achieved using the proposed approach for input frequencies higher than 267MHz for a 10-bit pipelined ADC with a maximum sampling rate of 50MS/s, while consuming 20% less power than a similar chip which required a front-end sample-and-hold. The third technique facilitates large ADC power reduction by replacing all opamps in a 10-bit 50 MS/s pipelined ADC with source followers, and uses a novel fully-differential passive gain technique to obtain an MDAC gain near 2x. Measured results from a prototype in 1.8V 0.18microm CMOS show the 50MS/s ADC to achieve a peak SNDR/SFDR of 58.2dB/66dB while only consuming 9.9mW for a figure of merit of 0.3pJ/step.