Design And Study On ESD Protection Devices For High Voltage Integrated Circuits

Electrostatic discharge(ESD) has become a major factor affecting the reliability of modern integrated circuits(ICs) and electronic products. Although ESD protections of conventional CMOS process IC products have been intensively investigated and widely applied, the ESD protections of high-voltage ICs fabricated in Bipolar-CMOS-DMOS(BCD) processes are still facing serious challenges. The important reason is traditional ESD protection devices such as diode, metal-oxide-semiconductor field effect transistor(MOS) and silicon controlled rectifier(SCR) cannot be directly applied to on-chip high-voltage IC ESD protection since the protected circuits work typically under severe conditions such as large voltage, high current, frequent plug-and-play and demanding electromagnetic compatibility. In this thesis, we focus on the features of high-voltage IC process and ESD designing requirements, study the important ESD protection methods for high-voltage power ICs, analyze the electrical characteristics and working mechanism of high-voltage ESD protection devices, and design high performance ESD protection devices, which are of good scientific significance and practical values for improving the reliability of high-voltage ICs.Firstly, the concepts of ESD test model, test methods and ESD design window are briefly introduced. The working mechanisms of basic ESD protection units, such as diode, bipolar junction transistor(BJT), gate grounded N-channel MOS(ggNMOS), SCR and LDMOS-SCR, are explained. By using the Technology Computer Aided Design(TCAD) simulation tools, the internal physical mechanism under ESD stress is analyzed, and the characteristics and various applications of different ESD devices are summarized.Secondly, the characteristics and working principle of dual-direction SCR(DDSCR) for high-voltage ESD protection is analyzed, and the difference between the n-p-n and p-n-p types DDSCR devices under the ESD stress is discussed. The ESD performance of the p-well grounded n-p-n type DDSCR is particularly investigated by transmission line pulse(TLP) tests and TCAD simulations, with an emphasis on the effect of grounded p-well on the ESD protection ability. Experiment results show that the holding voltage of the p-well grounded n-p-n type DDSCR increases from 12.8 V to 25.6 V. In addition, the effect of the p-well width on the leakage current of the n-p-n type DDSCR is also studied.Thirdly, a LDMOS-SCR with embedded reverse-biased diode is designed and fabricated using a 0.35 μm BCD process. Under the repeating non-destructive TLP test conditions, the test results show that, compared with the LDMOS-SCR devices prepared using the same process, the trigger voltage and ESD robustness of LDMOS-SCR with embedded reverse-biased diode does not change significantly, but the holding voltage increases from 2.7 V to 8.5 V. The same physical mechanism also exists between SCR and the SCR device with embedded reverse-biased diode. According to this understanding, a method is proposed by adding a floating p+ implanted region at the anode to form an embedded reverse-biased diode structure to increase the holding voltage of SCR or LDMOS. This novel method can provide a useful reference to the designing of high voltage ESD protection devices.Finally, a PMOS triggered high voltage LDMOS-SCR device is proposed. On one hand, the embedded PMOS can improve the trigger speed and reduce the trigger voltage of the LDMOS-SCR device. On the other hand, the PMOS can decrease the current gain of parasitic SCR, increase the holding voltage, and enhance the latch-up immunity of the device. By TCAD simulations, the working mechanism of the designed device under ESD stress is analyzed, and the feasibility of the proposed device is verified.