ESD Protection Design Of Narrow Window SCR Based On Various Process Platforms

Electrostatic discharge(ESD)is one of the main factors affecting the functions of integrated circuits(ICs)and even destroying the chips.Especially with the continuous progress of semiconductor manufacturing technology,the damage caused by the ESD has attracted wide attention,and the increasing necessity and importance of ESD protection are well recognized.Compared with the diode and gate-grounded NMOS,the silicon controlled rectifier(SCR)has the best current discharge capacity per unit area,and becomes one of the most popular ESD protection devices.Meanwhile,the poor transplantability of ESD protection solutions,the diversity of fabrication process,and the continuous reduction of the feature size of semiconductor technology aggravate the shrinking of ESD protection design window,and make the ESD protection design based on the SCR structure become more difficult.Therefore,in this thesis,various modified SCR devices with small snapback voltage are designed and manufactured based on the 0.25-?m Bipolar-CMOS-DMOS(BCD)process,0.18-?m CMOS process and 21-nm CMOS process,respectively.By the technology computer aided design(TCAD)simulations and transmission line pulse(TLP)tests,the internal operation mechanism and ESD performance of these protection devices on different process platforms are analyzed,discussed and optimized.The main content of this thesis can be summarized as follows.Firstly,the ESD protection design window of the protected circuits is defined,and the main electrical parameters of the ESD protection are introduced.The major ESD simulation software and testing techniques are then described.The operational principle of traditional SCR is briefly explained,and the basic design methods suitable for narrow ESD design window under the high-voltage(HV)and low-voltage(LV)processes are discussed.Secondly,two novel devices,N-type bridge SCR with embedded MOS(SCR_N_MOS)and SCR with embedded vertical NPN(VSCR),are designed based on the 0.25-?m BCD HV process.The snapback voltage of two SCR_N_MOS devices with different metal connections is small,which is 9.5 V and 8.3 V,respectively.However,their trigger voltage or holding voltage cannot meet the ESD design window of 5 V ICs simutaneously.Compared with the traditional SCR device,the snapback voltage margin of two VSCR devices with different anode layouts can be reduced by 21.0 V and 37.4 V,respectively,and the unit area ESD robustness can be improved by 8.0 times and 8.5 times,respectively.The ESD performance of the VSCR device with interfingered anode layout can meet the requirement of the ESD protection design window of 18 V ICs.Thirdly,two novel devices,the dual-direction diode-triggered SCR in double-well(DWDD_DTSCR)and dual-direction diode-triggered SCR in penta-well(PWDD_DTSCR),are proposed based on the 0.18-?m CMOS LV process.Both devices can realize the dual direction ESD protection with the strong unit area ESD robustness and a small snapback voltage.The voltage snapback margin of DWDD_DTSCR and PWDD_DTSCR is 0.1 V and 0.3 V under the positive ESD stress,respectively,and 0 V and 0.4 V under the negative ESD stress,respectively.However,the on-resistance of the both devices is large.Consequently,the influence of different layouts on the on-resistance of DWDD_DTSCR is studied,and an optimized solution for reducing the on-resistance of PWDD_DTSCR is proposed.Finally,two novel devices,the cascaded on-state PMOS and diode-triggered SCR(PMOS_DTSCR)and the one-directional diode-triggered SCR embedded in triple-well(TW_DTSCR),are developed based on the 21-nm CMOS LV process.Compared to the direct-connected diode-triggered SCR,the PMOS_DTSCR presents the zero snapback voltage characteristics,a small on-resistance of 0.7 ?,and the strong voltage clamping capability.Although the snapback voltage of TW_DTSCR is larger than the direct-connected diode-triggered SCR,it can be reduced from 0.6 V to 0 V by adjusting the spacing of doping regions in the p-well.Both the ESD design solutions based on the above fabrication process are suitable for the ESD protection of 1.5 V ICs.