Investigation Of ESD Protection For Typical And Power Integrated Circuit Process

In this dissertation, the research mainly focused on discussing on ESD phenomenon and seeking solutions for ESD issues in standard CMOS processes and high voltage BCD process. The research involves standard CMOS process in 0.18um,90um,65nm and 40nm, as well as 0.5um Bipolar-CMOS-DMOS process for high voltage and mixed voltage domain application. The discussion includes failure analysis and novel ESD device design. In his dissertation, the Barth 4002 Transmission Line Pulser(TLP) system is used for ESD schemes testing and verification. Related contents and conclusions as follows:ESD issues in low voltage CMOS processes. The thin oxide film failure in deep sub-micron processes is analysed. The research on ESD related prarameters concludes that the failure voltage of thin oxide film is influenced by ESD prarameters in time domain, as well as the thickness, area and lateral structure of the thin oxide film itself.ESD schemes for low voltage protection are discussed. The discussion is mainly on traditional diode, GGNMOS and SCR schemes, including theirⅠ-Ⅴcharacteristics, ESD rubustness and parasitic effects. The comparison of the three basic schemes provides theoretical support for the following research and design.LVTSCR for 65nm I/O protection is studied. The dimensions influence LVTSCR's ESD performance are studied. Based on these studies, one novel LVTSCR structure wih floating Nwell is proposed. This dissertation also invented a diode trigged LVTSCR for low voltage I/O protection.The diode string scheme for ESD protection is studied. The discussion mainly focuses on Darlington Effect and SCR operation mode in diode string. This provide theoretical support for the following research and design.An Improved DTSCR scheme is proposed based on the traditional DTSCR. With a low trigger voltage and proper holding voltage, the Improved DTSCR meet the basic requirements of the core circuit protection in 65nm process.The ESD related phenomenon in high voltage process is discussed. It is found that the trigger voltage of the LDMOS-SCR for high voltage ESD protection will "walk-in" in repeatedly TLP test. So the reliability of the value extraction by one-time TLP test is questioned.An efficient way to increase base width in SCR is proposed. By adding floating Nwell in SCR structure, the new solution provide high silicon area utilization ratio than traditional way by stretch base width laterally.