Optimized Design Of GGNMOS And SCR As ESD Protection Devices

With process featured-size shrinking and circuit complexity increasing instantly,the influence of electrostatic discharge（ESD）on IC（Integrated Circuit,IC）chip is more and more severe.However,most of the foundry just only utilized the elementary ESD protection device including diode string and MOSFET to protect their chips.They dissipate an amount of layout area to achieve the requirement of design,and thus increase the cost.In this thesis,various optimization ideas for conventional ESD protection devices are proposed based on Gate-grounded NMOSFET（GGNMOS）and Silicon-controlled rectifier（SCR）for better ESD performance in limited layout area.GGNMOS is the most compatible ESD protection device.The holding voltage（V_h）of GGNMOS is high enough to overstep the lower limit of the ESD design window.Nevertheless,the triggering voltage(V_t1)of the conventional GGNMOS normally dissatisfy the upper limit,and its robustness is weak.This dissertation focuses on optimizing the conventional GGNMOS for lower triggering voltage and better ESD robustness.The key parameter of GGNMOS was discussed based on a 0.55nm BCD process.Besides,three types of new GGNMOS（PB-NMOS）are proposed for better robustness.The new devices are fabricated in a 0.6μm BCD process and measured using the transmission line pulsing（TLP）tester.The test result illustrates that the optimal PB-NMOS possesses a 15.4%higher failure current(I_t2)and a 10%lower V_t1compared with traditional GGNMOS.SCR holds the best robustness of the fundamental ESD protection devices.While the high trigger voltage and low holding voltage limited its application.In the paper,the character and optimization methods of the conventional SCR are analyzed from macro-perspective and micro-perspective respectively.Besides,two types of new optimized SCR,based on a 0.18μm BCD process,are proposed with higher holding voltage to protect 5V power circuits.These devices were modeled and tested on TCAD simulation.The experiment results show that all of the new SCR devices hold 2.2 to 2.5times higher V_h and about 14%lower V_t11 than the traditional SCR,and thus they can effectively avoid the latch-up effects and triggering effects in 5V power circuits without extra layout area.