Research Of The Key Technology In Compact-low Jitter Fractional-n Frequency Synthesizer

Frequency synthesizer is one of the most critical circuit modules in integrated circuits(ICs).It can generate stable periodic signals,which can be provided as clock signals for digital systems or local oscillating signals for radio frequency(RF)transceivers.The accuracy,settling time,reference spurs,power consumption,and area are the critical index of frequency synthesizers.With the evolution of process nodes,the area cost of traditional charge pump phase-locked loops based on LC oscillators will account for larger proportion in the whole system.However,the phase noise performance of the ring oscillator with a smaller area is much worse than that of LC oscillator under the same power consumption.Therefore,the low jitter,compact frequency synthesizer has been pain more attentions in recent years.The main motivation of this dissertation is to design a low jitter fractional frequency synthesizer with ring oscillator.The main work and innovations of this dissertation is as follows.1)The system parameter design method and phase domain model of the type-II phase-locked loop(PLL)are analyzed.Then,the technology such as subsamplilng,sub-harmonic injection locking and open loop frequency synthesis which suitable for compact low jitter frequency synthesizer are analyzed in detail.And then,a fractional frequency synthesizer architecture with subharmonic injection locked phase-locked loop(SIPLL)and open-loop frequency synthesizer cascaded is proposed.The wideband characteristic of SIPLL achieves sufficient suppression of the phase noise of ring oscillator.The second stage uses an open-loop frequency synthesis system to achieve high frequency resolution,fast-frequency switching.The proposed architecture is verified through circuit and behavioral level simulation.2)Based on the phase-alignment theory of injection-locked oscillator,a linear model of SIPLL is established.A continuous-time frequency tracking loop of SIPLL based on sub-sampling phase detector(SSPD)is designed.3)A low-power,highresolution digital phase modulator(DPM)based on injection-locked ring oscillator(ILRO)is proposed in this dissertation.The dynamic range of porposed DPM is 2? and its phase resolution is 10 bits.Simulation results show that the differential nonlinearity(DNL)is less than 0.8LSB over the whole dynamic range.And its power consumption is 0.8mW when the input frequency is 450 MHz.An open-loop frequency synthesizer based on phase switching is designed with propoed DPM.4)A feedforward ring voltage controlled(FRVCO)oscillator insensitive to supply noise and process variation under near-threshold supply is proposed.A compensation voltage is obtained by detecting the varation of the MOS transistors' threshold voltage caused by process varation and supply noise.Then,the compensation voltage tunes the capacitive load of FRVCO to compensate the frequency drift caused by the above factors.The oscillator center frequency variation caused by the process varation is reduced from 38.3% to 1.5%,and the power supply sensitivity is reduced from 2.5 to 0.12.5)A two-stage ring voltage controlled oscillator with low power consumption and wide tuning range is proposed.A resistor between the input node and the inverting output node is inserted to enhance the oscillator frequency.Combining the current and cross-coupling feedback strength tuning methods,the proposed VCO achives rail-to-rail linear voltage tuning range.The measured tuning range of the VCO is 0.86GHz~1.38 GHz with less than 1.1mW power consumption.The proposed low-jitter,compact fractional frequency synthesizer is fabricated in TSMC 28 nm CMOS process.The area of the entire frequency synthesizer is 200?m×400?m.The mesurement results show that the output frequency range is 300MHz~540MHz,the frequency resolution is better than 1KHz.And the power consumption of the SILPLL is 0.6mW when the output is 440 MHz at 0.9V power supply voltage.In this case,the SIPLL achieves-100dBc/Hz phase noise at 100 KHz frequency offset,3.8ps RMS jitter performance and-230.6dB Figure of Merit(FoM).The proposed entire fractional frequency synthesizer consumes 2.7mW with 440.4MHz output frequency with-85dBc/Hz phase noise at 100 KHz frequency offset,17.6ps RMS jitter and-210.9dB FoM.