Research And Implement Of High Performance, Low Cost CMOS Frequency Synthesizer

Frequency synthesizer is one of the most important circuit blocks in ICs. It defines a periodic clock signal to drive digital systems or to up-converter and down-convert the wanted signals in wireless and wireline transceivers. The accuracy of this clock will affect or even decide the performance of the total system, thus high performance synthesizer is always a necessity.Beside the performance, design cost should be paid on equal attentions, for silicon proof consumes considerable time and money. The design cost is mainly from the occupied die area but unfortunately, the PLL figure-of-merit, which is usually used to compare different synthesizer designs, is even NOT related to the die area. The major reason is the huge performance gap between an area-friendly ring oscillator and its area-intensive LC counterpart, i.e. normally ring oscillator consumes 100x power to achieve similar performance as a LC oscillator at the same frequency. Actually the inductor in LC oscillator is treated as, "the last inductor" to implement an inductorless transceiver.The main motivation of this thesis is to solve the above issue, i.e. to implement high performance synthesizers without the need of any inductors. We start from the design of a 600 MHz sub-harmonic injection-locked ring oscillator, which shows-120 dBc/Hz and -130 dBc/Hz phase noise at 100 kHz and 1 MHz frequency offset, respectively. The excellent phase noise performance achieved from injection-locking is due to the extended filtering bandwidth to oscillator noise, which is the key in our following application based designs.For clock generation synthesizers, phase noise and frequency resolution is relaxed compared with LO generation case, thus this thesis proposes a uniformed design, i.e. a clock generator IP. The IP occupies 0.078 mm2 die area, and outputs 50-600 MHz clock signals with good jitter performance, duty cycle and stability. The IP can be directly employed in many different applications, avoids the need of ASIC designs.When fractional-N operation is need for the sake of fine frequency resolution, quantization noise induced by ΔΣM stops us from choosing a wide bandwidth to suppress oscillator noise. Moreover, the state-of-the-art synthesizer architectures, i.e. sub-sampling PLL, sub-harmonic injection-locked PLL, multiplying DLL as well as the designed sub-harmonic injection-locked ring oscillator, are all inherently limited to integer-N type operation. This thesis proposes to introduce a phase rotating, frequency multiplied DTC to the reference path of an integer-N PLL to get rid of this. The DTC is gain and range calibration free, and its quantization noise level is pretty low thanks to the high operation frequency of the AZM. Measurement results show the designed DTC achieves - 120 dBc/Hz in-band noise, and capable of generating 390-640 MHz output frequency with 0.3 kHz step. Quantization noise appears only over 20 MHz frequency offset, and the die area and power are only 0.257 mm2 and 6.3 mW, respectively. Treated as a tunable reference oscillator, this DTC simplifies the design of high performance fractional-N synthesizer to the design of a normal integer-N PLL. And when low cost is required, just employs ring oscillator in the integer-N PLL, whose bandwidth could be set up to 20 MHz to suppress the oscillator noise, will be enough.