Research Of The Frequency Synthesizer For 3GPP LTE And IEEE 802.11

With the application demand for wireless communications gradual transition from traditional voice to the growing data use,wireless communications system standard has been constantly evolving in the past two decades.So far,Long Term Evolution(LTE)developed by the Third Generation Partnership(3GPP)and IEEE 802.11 wireless LAN standard by the International Institute of Electrical and Electronic Engineering(IEEE)has become the two most important and popular wireless communication standard in the world.Benefit from the rapid advances in semiconductor manufacturing processes and technology,the wireless communication transceiver module system is developing in the direction of highly integrated,multi-band and multi-standard format.To support multi-band and multi-standard,the transceiver system needs to have a wide frequency tuning range with a strong anti-interference capability,and it must be able to quickly switch between different frequency bands.This requires a wide frequency range,good phase noise,fast locking time,small locking error,a large capturing range on the frequency synthesizer.Among many frequency synthesizer structures,Σ-Δfractional frequency synthesizer has the good phase noise,low spurious emission,and ease of integration with the digital circuit.It is also independent of channel spacing.These advantages makeΣ-Δfractional frequency synthesizer the most widely choice of communication transceiver system.Base on the requirement above,this dissertation presents a comprehensive discussion and study on the design of the frequency synthesizer.Firstly,the paper introduces the basic working principle and structure of the PLL frequency synthesizer,mainly focus on the mathematical model of high order passive filter charge pump PLL,derives loop gain,lock time,the stability of PLL phase margin and other performance parameters.Then,it described the sub-model circuits of frequency synthesizer as well as their working principle and key performance parameters.The paper also analyzed the noise sources of frequency synthesizer with its impact on the PLL loop and whole transceiver system.Regarding to the dynamic characteristics of the frequency synthesizer,this dissertation gave a detailed analys is and derivation given the initial status of tracking and capturing.According to the requirement from 3GPP LTE/LTE Advanced and IEEE 802.11ac communication standard,this dissertation presents the transceiver structure and breaks down the performance requirements for the fractional frequency synthesizer.The EDA software is used for the frequency synthesizer behavior modeling and system loop parameters design verification.After further breaking down the frequency synthesizer performance specification,the sub-circuits of the frequency synthesizer are designed in the next chapters.By using TSMC0.13μm CMOS process,this dissertation designs the Phase Frequency Detector(PFD),Charge Pump(CP),high speed Frequency Divider,dual-band LC Voltage Control Oscillator(LC-VCO),and digital circuits.PFD and CP have big impact on the noise floor and spurious emission performance of the frequency synthesizer.Based on the traditional edge-trigger PFD structure,this dissertation gives a high accuracy PFD design based on TSPC(True Single Phase Clock)D flip-flop,The PFD has a simple structure with low power consumption,wide phase range,zero phase dead zone advantages.Taking into account of the non-ideal factors of the charge pump and charge injection sharing problem,a self-biased technical error amplifier charge pump is proposed and designed in this chapter.A joint simulation result of PFD and CP show that the designed circuit has zero dead zone,the phase range,output range and other performance meet the system requirements.The VCO,which provides the frequency output of the frequency synthesizer,directly determines the tuning range and out-of-band phase noise of the frequency synthesizer.Compared with the classic LC-VCO with non-ideal RF performance,this dissertation uses a new LC-VCO structure with a switched cross-coupled switching pair,high linear ity varactor and noise filter ing technology to optimize the phase noise,power consumption,oscillation amplitude and tuning range.To achieve a wide tuning range,a band selected 4-bit switch capacitor tuning array is used in the core VCO circuit.The whole chip size is 1.11*0.98mm~2including the pads.The test results show that under a 1.2V supply voltage,the current comsumption of the VCO at two frequency bands are 3mA and 4.5mA respectively.The tuning range of the VCO is3.14~3.88GHz and 3.86~5.28GHz.On the oscillation frequency of 3.5GHz and 4.2GHz,the VCO phase noise is-123dBc/Hz and-119dBc/Hz at 1MHz offset.Fractional frequency synthesizer digital circuit mainly comprises a programmable frequency divider,Σ-Δmodulator,automatic frequency calibration module(AFC).As the programmable divider operates at the highest frequency in the PLL where power consumption is the largest part in the loop,reducing power consumption is the key to a programmable frequency divider design.This design uses cascaded 2/3 divider structure,progressively reduces the frequency to achieve an overall low power consumption.By taking advantage of theΣ-Δmodulator random output characteristics,the spurious emission of the fractional frequency synthesizer has been well suppressed,and noise shaping feature fromΣ-Δmodulator can also move the phase noise of the frequency synthesizer to high frequency band for easy filer ing in the PLL loop.Since the VCO switched capacitor array for each frequency band has been divided into 16 sub-bands,this requires automatic frequency calibration module(AFC)select VCO in the corresponding sub-band after dividing ratio being changed.The digital module workflow has been verified by a simulaiton,which show it meets the system requirements.