Compact modeling of nanoscale CMOS

The scaling of bulk CMOS technology results in incredible reduction of cost-per-computation with higher computational performance. It is conventionally achieved through the combination of thinner gate oxide, higher effective channel doping and shallower source/drain junction depth. However, these techniques are rapidly approaching material and process limits. The multi-gate FET such as FinFET has emerged as the most promising candidate to extend CMOS scaling beyond the 22nm technology node. The strong electrostatic control over the channel originating from the use of multiple gates reduces the coupling from source and drain. It enables the multi-gate transistor to be scaled beyond bulk planar CMOS for a given dielectric thickness.; A compact model serves as a link between process technology and circuit design. It maintains a fine balance between accuracy and simplicity. An accurate model based on physics allows the process engineers and circuit designers to make projections beyond the available silicon data for scaled dimensions and also enables fast circuit and device co-optimization. It is thus necessary to develop a compact model of multi-gate FETs for technology and circuit development in the short term and for product design in the longer term.; Full scale multi-gate FET compact models are developed. Unique device physics in the multi-gate MOSFET due to extra gates are studied and investigated. Modeling methodologies are proposed to incorporate these unique multi-gate physics in the compact model. Different flavors of the multi-gate FETs are modeled in two categories: the symmetric/common-gate multi-gate FETs and the independent/asymmetric multi-gate FETs. The complete multi-gate compact models are verified with TCAD simulation results and experimental data.; The performance comparison and design concepts of multi-gate-based logic and memory circuits are studied using the BSIM-MG model. The impact of the process variation can be tuned out by using back-gate tuning. The impact of back-gate length and misalignment on the threshold voltage is discussed.; In the sub-45nm CMOS technology regime, the impact of device variations on circuit functionality becomes critical. The scaling of the device geometry makes device characteristics more sensitive to the fluctuation of process steps. A novel methodology for generating Performance Aware Models (PAM) cards is presented for accurately predicting the statistical variations of VLSI circuit performance due to process variation. The PAM cards also improve the accuracy of Monte Carlo simulations by reconciling the physical and electrical-test variances.