Research On 60 GHz Phase-locked Loop In 40 Nm CMOS Technology

In the past few years,society has been radically changed by the rapid development of wireless communication technology.In the RF front-end circuit,Phase-Locked Loop is the key modules of wireless transceiver.Based on domestic chip design,chip manufacturing and chip testing,this thesis has realized the first domestic 60 GHz PLL chip of 40 nm CMOS process.Its power coms ? mption,phase noise and FOM have reached the international advanced level,which can contribute to China's RF chip localization ability.The main work and innovation of this thesis are as follows:(1)Research on 60 GHz RF Process Model.The best domestic technology manufacturer cannot provide the ADS library that use to "field analysis".Based on the research of interconnect skin effect,this paper successfully uses the method of"path analysis" to realize the localization of this chip.Therefore,this thesis firstly studies the performance of radio frequency transmission and establishes the corresponding SPICE simulation model.(2)Design and Implementation of 60 GHz Phase-Locked loop chip.In this thesis,a 60 GHz PLL chip with good performance is designed and implemented for the first time in the domestic 40 nm process.The measured phase noise is-92 dBc/Hz@1 MHz and-110 dBc/Hz@10 MHz,FOM is-170.7 dB.In the domestic technology,the PLL that designed by this thesis is the highest frequency and the highest performance PLL.(3)Research on higher performance VCO.In order to catch up with other international researchers,this paper has developed three novel technologies of 60 GHz VCO,which are low phase noise technology,anti-PVT technology,low power technology.Finally,the three innovative technologies have run in the silicon for verification:The low power VCO cons ?mes 10.4 mW power cons ?mption under 1.2V supply voltage.Compared to the traditional VCO design of the contrast experiment,in the case of phase noise performance is not affected,the power cons ?mption decreased by 23.5%.Compared to the traditional VCO design,the output signal power deviation of the six Anti-PVT VCO chips at different voltage is reduced by 1.8 dBm,and its FOM is optimized from-165 dB to-169 dB.Low phase noise VCO has achieved a phase noise of-85 dBc/Hz@1 MHz.Compared to the traditional VCO design of the contrast experiment,the phase noise is reduced by 4 dB.However,the power cons ?mption has a corresponding increase,so FOM keep almost unchanged.