Design Of Power Control And Phase-Locked Loop Modules For High-Speed CMOS Image Sensor

The CMOS image sensor market is growing continuously and rapidly.In the context of the Sino-US trade war,Chinese CMOS image sensor manufacturers are facing huge challenges and in the meantime,opportunities.Phase-locked loops and bandgap reference are essential circuit modules in a CMOS image sensor.The phase-locked loop plays a decisive role in the operation of the CMOS image sensor as an on-chip integrated clock signal generating circuit.The bandgap reference can provide voltage and current bias with a certain temperature coefficient for the chip,and also provide a current source for the phase-locked loop charge pump.It is an essential part for the normal operation of the phase-locked loop,so the power control module and the phase-locked loop are the research content of this paper.This paper starts with the basic structure of a CMOS image sensor,then designs a power control module including a bandgap reference and a phase-locked loop module in CMOS image sensor application.The proposed phase-locked loop circuit includes a single-loop charge pump phase-locked loop And a dual-loop charge pump phase-locked loop.This paper summarizes the general design concerns and procedures of universal bandgap reference and phase-locked loop.By modifying specific parameters of the proposed circuit topology,compatibility in different processes can be achieved.The power control module and phase-locked loops mentioned above have been tested under different process conditions at different foundries,and can guarantee the operation of CMOS image sensor chips in different products.This paper analyzes the circuit architecture and requirements of the power control module in detail and analyzes the indicators we need to focus on and design principles of the bandgap reference,and thus designs a bandgap reference that meets the application requirements.This paper gives the post-simulation results of the designed bandgap reference source under four process conditions of three foundries,which have taped-out and shown no bad effect on sensor operation.They have been applied in mass production chips.In this design,we ensure that the temperature coefficient is the first order priority,and make sure the output reference voltage is around 1.2V.As the length limit,this paper only gives the technical specifications of the designed phase-locked loop under the DB 0.11μm for CIS 1P3M process.The whole CMOS image sensor test results show that the designed single-loop charge pump phase-locked loop and dual-loop charge pump phase-locked loop can work normally under the voltage combination of 1.8V or 2.8V analog power supply voltage and 1.5V or 1.8V digital power supply voltage.Both of them support 6-40MHz input reference frequency.According to the application scenario,27MHz is commonly used.By configuring the divider division ratio,both can achieve a tuning range of 0.4-1.5 GHz.Post-simulation shows that the voltage controlled oscillator output 48%-52%duty cycle at any PVT condition at 945MHz or 1GHz oscillation frequency.Post-simulation shows that at a working frequency of 945MHz,the single-loop phase-locked loop has a settle time of 3μs,the RMS value of TIE jitter is 23.3ps,the RMS value of Period jitter is 1.22ps,the RMS value of Long Term jitter is 33.5ps,the power consumption RMS value is 2.875m W and occupied 0.0571 mm~2 chip area.The dual-loop phase-locked loop has a settling time of 25μs.The RMS value of TIE jitter is18.2ps,the RMS value of Period jitter is 1.21ps,the RMSv alue of Long Term jitter is26.4ps,the power consumption RMS value is 3.058m W and occupied 0.0397 mm~2 chip area.This paper proposes an innovative bandgap reference circuit topology.It can achieve the expected technical indicators by trimming specific device parameters under four different processes at three foundries to achieve process compatibility after tape-out verification.Innovatively proposed a dual-loop PLL structure.Compared with the traditional single-loop PLL,its noise performance is better and the layout area is saved by about one-third,which greatly saves chip resources and is beneficial in reducing costs.The proposed dual-loop PLL can be adjusted to achieve process compatibility by changing the specific device parameters and is verified by both simulation and tape-out.