Based On The 65 Nm Cmos Technology Of Millimeter Wave Phase-locked Source Study

With the fast development of semiconductor process, the60GHz ultra-high-speed short-range wireless communication based on CMOS process has become a research hotspot. Phase locked loop (PLL) is the key block of the transceivers, which has a very important significance. Therefore, aiming at60GHz ultra-high-speed short-range wireless communications applications, according to the receiver system performance requirements on the phase-locked loop, the loop filter parameter is designed by MATLAB, the behavioral modeling is simulated by Simulink. Then the module circuits are designed, such as voltage-controlled oscillator (VCO), frequency dividers, phase frequency detector (PFD), charge pump (CP). The article’s main contents are as follows:1) In system design, the transfer function of the loop is derived and the parameters of the loop filter are calculated by MATLAB. The behavioral model of the phase locked loop is simulated by Simulink. Thus, the settling character and the parameter of module circuits are obtained.2) In the part of the loop noise analysis, by analyzing the noise transfer functions of each circuit modules, the transfer characteristic of the noises is acquired.3) In the design of module circuits, the NMOS cross-coupled structure is adopted to realize VCO circuit. The PMOS transistor is used a tail current source to reduce the phase noise. Two stages buffers are used at the output of the oscillator to improve the output power and reduce the load-pull effect. The tail current source of the first stage current mode logic frequency divider is omitted to enable it to work at low supply voltage. The shunt peaking inductor is introduced in CML to increasing its operating frequency. Reset delay method is adopted to overcome the dead zone in the PFD. The current steering charge pump is used to reduce the switching time, thereby increase the operating frequency of the charge pump.Finally, the PLL circuit is simulated based on UMC65nm CMOS process. The phase noise of the VCO is-90dBc/Hz@1MHz offset. The PLL can be locked from29.5GHz to31.7GHz. The PLL including buffers consumes48mW from1.2/0.7V supplies. The output spectrum shows the reference spur lower than-23dBc. The simulation shows that the parameters of the phase locked loop achieve the requirement of the60GHz ultra-high-speed short-range wireless communication receiver, which verifies the rationality of design and correctness of theoretical analysis in this article.