Research Of Low-power Two-Point Modulation Transmitter And High-Energy-Efficiency ADC

With the continuous development of wireless communication technology, wireless devices have been widely used in people’s daily life and industry control. The requirements for these devices have changed from functionality with proper performance to the improvement of users’experiences. Battery lifetime is one of the most important one, so low-power, high-performance and low-cost have been the key competency of the product. Frequency source (Voltage Controlled Oscillator) is a key-building block of RF circuits. It has an intrinsic voltage-to-frequency transformation characteristic. We could make use of this characteristic to realize frequency modulation and voltage-domain to time-domain transformation. We focus on the low-power, high-energy-efficiency realization of the two proposed systems, which are all based on frequency sources. The theoretical analysis and chip measurement are all well verified.Zigbee protocol has properties of low-cost, high-capacity, and its data-rate and communication range are250kbps and100meters respectively. These make it very suitable for wireless sensor applications. We implement frequency modulation with two-point modulation of closed-loop PLL based on direct modulation of VCO. This structure minimizes system-complexity and is low-power-featured, not like convectional mixer-based structure. Calibration of mismatch between modulation paths is needed usually. We propose adoption of a capacitance-desensitization technique to minimize mismatch of varactors and an interleave-biased technique to enlarge varactor’s linear range by linearizing the voltage-to-frequency tuning curve of oscillation tank. This low-power low-cost implementation of two-point modulation transmitter does not need extra calibration circuits and meets the specification requirement of Zigbee standard. We also use dead-zone-free phase/frequency detector and linear, low-noise charge pump to avoid noise folding of Sigma-Delta modulator. And capacitance compensation technique is used by power amplified to increase gain and stability. The all proposed techniques are verified through0.18μm CMOS process.Supply voltage decreases with CMOS scaling, this leads to decreasing of voltage resolution of traditional voltage-domain ADC. It would suffer more from device noise. Much more complex circuits are needed to suppress noise for high resolution. Lucky enough is that parasitic effects decrease too with CMOS scaling. That means transmission delay is lowered of typical devices, hence time resolution increases. We make use of voltage-to-frequency transformation characteristic to modulate voltage signal to time signal. But the linearity of voltage-to-frequency transformation curve limits the system SNDR performance; traditional ways are to use close-loop feedback or back-ground calibration. These would increase system-complexity and power-consumption. We propose using Asynchronous Sigma-Delta Modulator to modulate voltage to pulse-width of square-wave, and since there are two voltage level of square-wave, the voltage-to-frequency tuning curve of VCO is always linear. Another solution, which combines linear voltage-to-current conversion and linear current-to-frequency conversion techniques, is proposed to minimize non-linear effect by adding in degrees of design freedom. The low-power and high-energy-performance-efficiency time-domain ADC is verified through simulation and measurement in65nm CMOS process.