Design Of 13GHz Voltage Controlled Oscillator And Phase-locked Loop

In wireless transceiver, frequency synthesizer is a key module, which can provide a stable, programmable, low-noise local oscillator signal. The performance of the system is decided by the function of frequency synthesizer. In the frequency synthesizer based on the phase-locked loop, the voltage-controlled oscillator and divider is the RF modules, whose performance is the key and prerequisite capable of stable operation for frequency synthesizer.Firstly,This paper introduces the features and indicators of the frequency synthesizer in the communication system and determines the structure of the frequency synthesizer before introducing phase-locked loop structure, working principle and linearization and noise model. Then the paper performs loop design parameters based on the maximum phase margin method and comprehensive consideration of spurious noise and other indicators. Secondly, it introduces the VCO type and performance indicators, resulting in determining the structure and parameters of LC-VCO module circuit. At the same time, the type of pre-two divider is detailed and the structure is determined. Theoretical analysis and parameter design is carried on and the layout, simulation results and the measured results is given. Finally, the behavioral modeling of the other modules (PFD/CP, the divider) is built and additional modules (AFC, SPI, timing control module) is designed with Verilog. The mixed analog-digital simulation of the entire frequency synthesizers is made, with the simulation results given.Based on TSMC 0.13-um 1P8M CMOS process, design of a full NMOS LC-VCO and pre-divider based CML latch is designed. Then the circuit simulation, layout post-simulation is carried on and the chip is measured. Meanwhile, the paper completed the digital-analog mixed simulation of the integer frequency synthesizer. On-chip test results show that under 1.2V supply voltage, The frequency band can be tuned 12.4～15.4 GHz continuously. The VCO differential output power reaches 0.66 dBm at 15.2 GHz and achieves phase noise of-119.74 dBc/Hz at 1 MHz offset from 15.2 GHz. The chip area of the VCO including all bonding pads is 0.56x0.84 mm2; Pre-divider operating frequency range of 11-21GHz and the self-excitation frequency is 17GHz. The core area is approximately 30×25um2; In mixed analog-digital circuits, SPI woks 3.2us, AFC about 6 us. After choosing the tuning curve, the PLL work around 14us.Therefore,the locked-time is 24us,when the tuning voltage amplitude is 0.75 V, with the fluctuation about 0.9mV.