| Digital-to-Analog Converter (DAC), which transfers digital codes into analogsignals, is the bridge connecting digital world and analog world together. With theextensive application of wireless communication systems, it has been a trend that thedate transfer rate and the signal bandwidth are increasing. DAC has become anindispensable module of modern wireless communication system, and is heading forthe direction of high speed and high resolution.A12-bit200MSPS segmented current-steering digital-to-analog converter isproposed in this paper, and it is implemented under the Global Foundry (GF)0.18μm1P6M CMOS technology. To achieve tradeoff among performance, silicon area,complexity and power consumption, a split with5thermometer most significant bits,4thermometer upper least significant bits and3binary lower least significant bits ischosen for this DAC. A series of binary-weighted subsidiary DAC is implemented tocalibrate the5MSB current source array due to its rigorous matching requirement.Thus, the static linearity is obtained without occupying clock period or increasingmuch additional circuits. Some of the key modules of the DAC including bandgapreference, voltage-to-current converter, current source array, switch array andcalibration circuit are analyzed in details in this paper. Moreover, the design of thelayout is introduced at length, including the utilization of the hierarchical symmetricswitching scheme and H-shaped layout of power line and digital signal line toguarantee and improve the performance of the DAC.The power supply for analog part of this chip is3.3V, and digital part1.8V. Thecore area of this chip is less than1.44mm2. The preliminary test results show that theDifferential Non-Linearity (DNL) and the Integral Non-Linearity (INL) is±0.5LSBand±0.7LSB respectively, and the Spurious Free Dynamic Range (SFDR) is75dBat1MHz signal frequency and200MHZ sampling frequency. Therefore, it proves theproposed DAC basically meets the design specifications. |
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