Research On Test Stimulate Compression For Digital Intergrated Circuits

As the size and the complexity of the Very Large Intergarted Circuits (VLSI) continue growing, the test data volume had been increasing dramatically. High test data volumn leads to an increase in testing time, and may exceed the limited memory depth of the automatic test equipment, and also leads to very high test power. Thus, how to make the test data volume as small as possible has become one of the challenges for VLSI testing. Test data compression offers a promising solution to the problem of increasing test data volume. This dissertation focuses on the test data compression for digital circuits, aiming at the test data volumn and test application time reduction with low hardware cost. The main works are presented as follows:(1) Proposes a novel test data compression scheme which uses double prefixes to encode test sets without losing fault coverage. The technique uses two prefixes to identify codewords which decreases the longer run-length’s codewords compared with conventional code-based compression solutions. Two kinds of test sets are used in the experiments, the first kind are gotten from test set regeneration, and the second kind of test sets are obtained from scan partition scheme. Theoretical and experimental results both show the efficiency of the proposed scheme.(2) Proposes the selective sparse storage scheme for test data compression. The Test sets are partitioned into four kinds of blocks with uniform length, all-0blocks, all-1blocks, sparse blocks and characterless blocks. Blocks are encoded appropriately based on the occurrence of them. Two algorithms are proposed for how to select the sparse blocks from test sets. A theoretical analysis for the selective sparse storage shows the new compression technique outperforms the conventional test data compression approaches. Experimental results illustrate the flexibility and efficiency of the new method, which is consistent with the theoretical analysis(3) Proposes a new test data compression scheme using interval broadcast scan. The code-based compression schemes adapt to circuits with single scan chain, the test time would incease when it used on circuits with multiple scan chains. To solve this problem, the interval broadcast scan allows broadcast identical test data to several scan chains whenever the cells in the same depth are compatible. Thus, it efficiently utilizes the compatibility of the scan cells among the scan chain segments, increases test data run in broadcast mode and reduces test data volume and test application time effectively. It does not need complex compressing algorithm and costly hardware. Experimental results demonstrate the efficiency and versatility of the proposed method.(4) Proposes a design for testing architecture for test data compression. The single scan chain is divided into multiple scan chains in design phase. The test generation is operated in two stages. It first generates for broadcast scan mode. Then, for all remaining undetected faults, a nonfilling ATPG is used to produce a partially specified test set. The test sets are operated in three test scan modes. Compared to the Illinois scan architecture (ILS), the compression ratios in its worst cases are same as the ILS’ with the same hardware cost.(5) Proposes a virtual scan chain reorder technique which targets on test compression. Scan chain reordering scheme could be used for test compression by making the corresponding test set more easily compressed. However, it may adversely affect scan chain routing by creating very long routing path and modifying signal delays. To achieve high test compression using scan chain reordering without routing costs, the approach uses a RAM-based module to control the orders of scan cells in circuits. The scan cells can be virtually arranged into any order for different compression schemes. Experimental results show that the proposed method can raise the compression ratio efficiently.