| Design for test can effectively reduce test time and improve the fault coverage,but with the rapid increase of IC scale and complexity,the complexity of IC test is greatly increase,and design for test puts forward higher requirements.The test compression technology based on scan chain can further reduce the test time and test data volume,and does not increase the number of test ports.It has limited influence on the area and power consumption of the circuit under test,so it is widely used in testing.However,with the increase of the compression ratio of the compression scan chain,the fault coverage of the traditional compression scan chain decreases and the wire length of the compression scan chain increases.This thesis is based on a 1.54 million standard cells,140000 flip-flop,working frequency of 2.3GHz,RISC-V core design reserved 8 pairs of scan I/O ports.Design for test architecture that can be used for internal core test,external test and at-speed test is designed and implemented.Firstly,the core wrapper and the wrapper instruction register based on IEEE 1500 standard are designed and implemented,which can shield the influence of external circuits on the external test,and facilitate the top-level design to flexibly schedule the test.Then,the on-product clock generation circuit is designed and implemented which can generate at-speed test clock pulse to realize at-speed test.Finally,the compression scan chain test with 50 times compression ratio and 8 pairs of test I/O ports is adopted to reduce the test time and test data volume.At the same time,with the increase of the compression ratio of the compression scan chain structure,the wire length of the compression scan chain structure increases and the fault coverage decreases obviously.In this thesis,the 2D compression scan chain test based on grid cell network structure is proposed to reconstruct and reasonably plan the distribution of compression and decompression circuits to reduce the wire length.By using sequential decompression circuit,the problem of coverage decrease in high compression ratio can be alleviated.A multi-test mode testing method is proposed and analyze the fault coverage results to improve the fault coverage.A new structure combining grid cell and low power gating is proposed,which can reduce test power effectively.The relationship between compression ratio and test time,fault coverage and interconnect length of compression scan chain is studied to further reduce test time on the premise of ensuring fault coverage and wirelength.(1)The stuck-at fault coverage of traditional compression scan chain test is 98.25%,the transition fault coverage is 92.99%,and the number of test patterns is 28538.(2)The stuck-at fault coverage of 2D compression scan test is 98.25%,the transition fault coverage is 93.05%,and the number of test patterns is 26962,and compared with the traditional compression scan chain,the number of test patterns is reduced by 5.52%,and the wire length of the compression scan chain is reduced by 14.36%(3)After the fault coverage optimization,the stuck-at fault coverage of traditional compression scan chain test is 99.61%,and the transition fault coverage is 97.44%.The stuck-at fault coverage of 2D compression scan chain test is 99.62%,and the transition fault coverage is 97.46%.(4)Through grid cell with low power gating and scan shift switching percentage constraint,the test power consumption is reduced by 32.41%.(5)To achieve 400 times compression ratio of 2D compression scan chain,the test time is reduced up to 46.9%.Under the same compression ratio,the wire length reduced by up to 48.5% compared with traditional compression scan chain.The 2D compression scan chain based on grid cell network structure proposed in this thesis can alleviate the problems of decreasing coverage and increasing wire length under high compression ratio.At the same time,the method of optimizing fault coverage,test power consumption and test time also has certain reference value in realizing high quality and low cost IC test. |
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