Studies On Low Power Test Method Based On Scan Chain Reordering Technique

Integrated circuit(IC), which has been widely used in all trades and professions,is considered as the heart of the electronic equipments such as computer, electronicproduct and so on. With the scale of the integrated circuit becomes larger and largerand the structure of the integrated circuit becomes more and more complicated, thetest for integrated circuit becomes more difficult. As a result, the proportion of testcost becomes greater and greater, even more than the manufacturing cost.Scan-based test is one of the usually adopted test strategy, and its powerdissipation during test can be significantly higher than that during normal operation.The power dissipation of scan-based test mainly comes from following three aspects:(1) the power dissipation generated by test patterns during scan shift-in process;(2)the power dissipation during capture cycles;(3) the power dissipation generated bytest responses during scan shift-out process. With the scale of the integrated circuitbecomes larger and larger, power dissipation in scan-based testing is becoming amajor concern for research.In order to solve the above problems, this thesis presents a low power testmethod based on scan chain reordering technique. In the proposed method, we put thescan cells which have high probability of having the same bits together as much aspossible to increase the correlation between adjacent scan cells. The number oftransitions in the scan chain during scan shift cycles is reduced. We also consider theaffection of each scan cell to its fan-out combinational part and put the scan cellswhich have high effect on power dissipation of internal circuit to the position near toscan-in pin. The number of transitions in the combinational part during scan shiftcycles is also reduced. In addition, this thesis considers the wire length and exploresthe tradeoffs between wire length and test power dissipation.Finally, simulation experiment is performed to evaluate our proposed method.Experimental result shows that this thesis achieves the effective trade-off between testpower and wire length. Compared with previous work, if we only consider the power,the test power is reduced4.4%and wire length is reduced0.2%in average; When thetrade-off parameter α is0.6, both methods have almost the same test power while thewire length is reduced57.0%in average in our proposed method.