Research On Test Data Compression Of SoC By Coding Based On Extended Prefix And Grouping

Along with the development of integrated circuit manufacturing craft, the number of transistor in single chip is increasing. Due to integrating various intellectual-property (IP) cores, the function of SoC is developed strongly. However, with the increase in the number of IP cores integrated, test data volume and test application time grows quickly. Thus the test cost continuously rise because ATE(Automatic Test Equipment) is becoming more and more expensive with the increasing of frequency, bandwidth and memory.It is becoming more and more difficult to solve the conflict between increasing test data volume and limited bandwidth of automated test equipment (ATE). Coding method is one of the promising methods to solve this conflict under an acceptable cost. It reduces the transferring test data and the test application time effectively, and can ease up the contradiction between the great number of test data and the limited bandwidth of the test equipment. The dissertation makes research in test data compression of SoC by coding.After analyzing some traditional coding method, extended prefix coding is presented. Based on test data analysis, it has been observed that tests set contain a large number of runs of 1's in addition to runs of 0's. The extended prefix code is a variable-to-variable run length code based on encoding both runs of 0's and 1's. The code word consists of prefix and tail. It uses extended prefix to indicate the type of run. So it doesn't add an extra bit. The don't care bits can be fixed with an excellent method, so that the test power can be reduced. Due to using a special shift counter to simplify the control circuit, the decompression circuit can be implemented easily and the hardware cost is low. Theoretical analysis and experimental result show that the proposed scheme can provide high compression efficiency and low test power.A test data compression scheme based on array compatibility in grouping of multiple scan chains test set is presented, which makes a good tradeoff among many aspects, such as compression ratio, hardware spending, and decompression protocol. A test set is divided into several groups after it has been formatted according to multiple scan chains. Then the several vectors in the same group are compressed to one by using array compatibility method. The proposed method makes use of the relativity of test vector and don't care bits in test set effectively. It is different from some traditional run length code. Experimental results indicate that the proposed method has high compression efficiency.