ECL Sequential Circuits Design Based On Parallel-Or Clock Structure

In this dissertation, we mainly discussed the design method of ternary ECL sequential circuits. The new clock structure—parallel-or clock structure was presented to design different types of latches and triggers. Also, we use the state trigger to design sequential circuits.First, after analyzing its principle and electric character, we introduced the former improvement about the ECL circuits, especially the algorithm of switch level ECL circuits design characterized by the Boundary_addition-Minimization structure, and complemented the algorithm.Then, based on the algorithm of switch level ECL circuits design characterized by the Boundary_addition-Minimization structure, we analyzed the characteristic of the D latch, and designed the new ternary D latch with the parallel-or clock structure. We also designed the ternary T latch, ternary principal and subordinate trigger and duplicate D latch, and gave the Pspice simulations. The difference of principle between the new and old clock structure was analyzed then.At last, the behavior of the sequential circuits was analyzed, and the state trigger was used to design the sequential circuits. The sequential circuits were designed based the parallel-or clock structure. The issues in the flow, for example, the reverse state coding were analyzed to compare the difference between the new and old design method. Then the design flow was described by examples.