Research Of Clock Edge Control Technique And Low Power Flip-Flop

The speed, scale and performance of integrated circuit developed rapidly since its birth. In the past, the major concerns of the IC designer were speed and area. However, with process scaling, the power consumption of IC continues to grow. In recent years, power consumption has become another key issue, and it is being given comparable weight to speed and area in IC design. Thus, the research of low power design is very important.In CMOS circuits, decrease the number of internal nodes and their activities will effectively reduce the power consumption. The clock is considered to be a major contributor to the power dissipation of digital systems, because it is the only signal that switches all the time, and tends to be highly loaded. Studies indicate that the clock consume a large percentage of the system power. Therefore, reducing the clock power consumption can significantly reduce the power dissipation of digital systems. In this thesis, the clock edge control technique is proposed for the first time. By blocking the redundant clock transitions, the redundant behaviors of the circuit are reduced. What's more, the circuit structure can be simplified. Compared with the clock gating technique, the clock edge control technique has a wider range of applications. The clock gating technique is merely applicable to single edge-triggered flip-flop. It is a special kind of clock edge control technique. The flexible clock gating technique is proposed in this thesis, witch is easier to understand and could achieve a more optimal low power design. It blocks the redundant clock according to the actual situation, and some redundant clock needn't be blocked if the control circuit is too complex. In the next chapter, the clock edge controllable dual edge-triggered master-slave flip-flop is proposed. What's more, a novel method for low power sequential circuit design using alternate blocking technique is also proposed. And the redundant clock could be blocked in dual edge-triggered master-slave flip-flops for the first time. At last, the clock edge controllable single edge-triggered pulsed flip-flop and clock edge controllable dual edge-triggered pulsed flip-flop are proposed in this thesis. A large percent of power will be saved, because a lot of redundant behaviors are restrained.The design examples demonstrate that the proposed clock edge control technique is advanced and practical, and could efficiently reduce the system power dissipation. All the proposed low power flip-flops are simulated by HSPICE. Simulation results show that these flip-flops have correct logic function and simple structure, and could achieve large energy saving compared to the traditional flip-flops.