Research On Analog-front-end Key Technology For CCD High Defination Image Processing

As one of the most important image sensor today, CCD(Charge Coupled Devices) has been widely used in many civil and military fields such as high definition digital camera, digital video camera recorder,remote sensing and metering,astronomy measurement,aviation and space technology,target distinguish, etc. CCD image processing system include CCD array, AFE(Analog Front End) and digital processor, in which the AFE is the key part to convert the original CCD analog signal to digital signal. The performance of AFE determines the image quality. Its key technologies contain image signal processing, digital and analog mixed signal system top level design, high speed high resolution analog to digital converting. The research of AFE has become one of the central issue in high definition image processing and microelectronics fields.In this dissertation, 12bits 100MHz AFE system structure, analog to digital converting and key blocks are studied for 1024×1024 pixels and 100 frames per second CCD high definition image system.Based on the principle of double sampling theory and charge conservation, a CMOS switched capacitor anti-alias filter with 5th-order elliptic lowpass structure is presented, which can filter outside bandwidth noise in image signals effectively. So the quality of input signal to ADC is improved. The double sampling topology breakthrough the limitation of op amp unit gain bandwidth and slew rate, and the high frequency performance of the filter is improved.Combined Cascode Miller with output zero pole compensation, a novel frequency compensation for rail to rail voltage buffer is presented. This method can reduce the compensation capacitor, as well as ensure the op amp to operate stably in common input range without increasing the circuit complexity. This buffer can realize both high accuracy signal transfer and enough driving ability.On the basis of the system performance requirement and power optimization method, 12bits 100MHz Pipeline ADC architecture is built. It includes 9 stages with (4, 2, 2, 2, 2, 2, 2, 2, 2)resolution distribution. According to the analysis of technology tolerance, the affects of device dismatch to S/H and MDAC power dissipation are given. A capacitor dismatch self-calibration proposal for MDAC is presented. By this method, the capacitor dismatch in MDAC is calibrated. So the capacitor array can realize higher resolution with smaller size. The size of total capacitors can reduce to 50%, and the power dissipation of S/H and residual amplifier can reduce to 25%, the DNL and INL are improved as well.High linearity sampling switch, S/H circuit and voltage reference for Pipelined ADC are studied and optimization schemes are presented correspondingly. Three kind of high performance S/H configurations are presented: NFDSS bootstrapping switch, CGFF two stages full differential op amp with high gain and large bandwidth, CDS S/H circuit with low gain error. The simulation results show that all of the three configurations are satisfied with the requirement of 12bits 100MHz S/H.Only using Cascode current mirror to generate reference voltage, a bandgap voltage reference without op amp is designed. Also, combining resistor trimming with digital trimming technologies, 2th-order temperature compensation is realized. In -40℃～135℃temperature range, the temperature coefficient under TT model is 1.7 ppm/℃. When the signal frequency are DC, 1KHz and 100KHz, the power supply rejection ratios are -95.4dB, -92.4dB and -56dB correspondingly.Based on the layout design principle of high speed digital analog Mixed-Signal IC, the layout of AFE is designed with standard 3.3V 0.35μm AMS CMOS process. Total die size of this AFE is 3673μm×3735μm. Simulated with Cadence simulator after LPE, the results show that, this AFE achieves 12bits resolution, 100MHz sampling rate, DNL≤±0.4LSB, INL≤±0.4LSB. SFDR is 82.4dB at Nyquist frequency. The total power dissipation is 530mW. All the performances are satisfied with the requirement of CCD high definition image processing, which verifies the theories and simulation in this dissertation.