Research And Design Of The Analog Front End Of CIS Based 4T PPD Pixel

CMOS image sensor, which is a important branch of the solid-state image sensor, have more and more advantage in power assumption and integratability to replace the leadership of CCD image sensor. The higher pixel noise is always considered as the worst defect in all of the imaging characteristic and directly affect the high-accuracy design of the analog front end (AFE) in the CIS system. This thesis accomplish a low voltage ,high accuracy, 4T PPD pixel-based AFE with top-down desigh technology.Firstly the noise canceling mechanics in the physic design and time sequence of the 4T PPD pixel is reseached.According to the sequence feature and systemic specification requirement ,a simple feasible double storage node readout circuit is designed.Then the systematic design of"Relay Race"SC-PGA—the most important module in the AFE—is discussed and focused on the trade-off of the power assumption,accuracy and robustness in consideration of the 1.8V power,10 bit accurary amplification and 7 bit gain control.Finally,the circuit design of previous system is completed and simulated using the SMIC 0.18um Mix-signal Library. In the segment of simulation, these key gain stepping state and the overall systematic testing are highlighted.The result indicate the following conclusion: comparing with the traditional single node circuit,the double storage nodes readout circuit have a smaller power occupancy and a wider dynamic range;the"Realy race"SC-PGA can attain the 10 bit accurary and switch the gain step smoothly and equallyThe innovation of the work is aimed at the presentation and achievement of the"Relay Race"gain stepping scheme and"binary+thermal"mixing coding of capacitor array. Comparing to the original"Coarse+fine"scheme and signal coding method, the new ones are good at the trade-off of accurary and robustness and reduce the mass of wires and corresponding capicator mismatch,which is suitablt in the implementation of SC-PGA.