Research On All Digital Phase-locked Loop Technology In Digital Rf

When we try to apply software defined radio at radio frequency, how to realize the reconfiguration of RF ciruits is a challenge. And the implementation of traditional RF circuits in deep sub-micron CMOS process aslo has many challenges due to the scaling of voltage headroom, swichting noise and so on. Digital RF is a novel solution to solve those problems. All digital phase locked loop (ADPLL) in digital rf, which is presented recently, is one of the most important parts in digital RF. ADPLL not only can be used to built a generalized modulator, which can produce various RF modulation signals, but also can synthesize the local oscillation signals for receivers. In the dissertation, the ADPLL in digital RF and its some important modules are studied and the main contributions of the dissertation are as follows:1. A set of behavioral voltage-domain models based on Verilog-A language is presented in the dissertation. The models of the loop can be simulated fastly with current personal computers. The dynamic and stable characteristic of the closed loop, which is used to optimize the loop in system level at the early stage of the design, can be predicted by processing the simulation data with matlab. Furthmore, the characteristic of the loop is studied and a self-adaptive loop filter for II type loops is given. By using this kind of loop filter, the loop not only can lock fastly but also has better performance of phase noise.2. LC-based digitally controlled oscillator (DCO) is a critical part of ADPLL and its frequency resolution determines the performance of the loop.To enhance the frequency resolution of DCOs, a digitally controlled varactor structure based on mismatched capacitor pairs is proposed in the dessertation. In the structure, the minimum effective switched capacitance of CMOS varactor can be reduced, and thus the frequency resolution is enhanced. Finally, the DCO based on our structure is implemented in SMIC0.18 and simulated in Spectre. The results show that the frequency resolution can be improved dramatically without dependence on the feature size of the given process. 3. A time-to-digital converter (TDC) with high resolution, in which the delay cells are built only for the rising edge of the input signals, is proposed in the dissertation. The toal delay in the cell can be reduced to less than half the delay of traditional systems by choosing appropriate sizes of those transistors. Simulations show that the resolution can then be dramatically improved. To improve the resolution in serval picosecond level, interconnect lines of integrated circuits are used to construct a time interpolation circuit of TDC.4. The accuracy of interconnect delay estimations can be improved by the method presented in the dessertation, in which the first two moments are obtained with ABCD matrix and the total interconnect delay is divided into the electromagnetic propagation delay and the interconnect rise/fall time delay for more accurate estimation. Simulation results show that the method share the same accuracy with traditional methods when rise time delay is much longer than transport delay and more accurate when the two are of the same order.