Design And Research Of All-Digital Phase Locked Loop

Phase-locked loop is widely used in a variety of communication systems to generate clocks for system synchronization or recover timing information from incoming data streams.Cellular phones, computers, televisions and radios are just a few examples that rely on PLLs for proper operation. With such a broad range of applications, PLLs have been extensively studied in literature. With the development of SOC, low-power and high-performance became the main challenges for PLL design. Recently, however, many researches have been focused on ADPLLs because of their scalability, flexibility and higher noise immunity.To achieve jitter performance comparable to analog PLL, quantization error should be sufficiently reduced by improving the resolution of time-to-digital converter(TDC) and digitally-controlled oscillator(DCO). In order to improve the resolution of TDC and DCO,this paper full-custom designed a time amplifiers based sub-exponent TDC with a minimum resolution of 1.25 ps and a total conversion range of 2.5 ns. In addition, this paper also designed a high frequency ring-based DCO with a wide frequency range and fine resolution.Both wide frequency range(500MHz-1.55GHz) and fine resolution(1-8ps) are obtained using a cascading structure consisting of a coarse delay chain and an interpolator.Based on the full-custom designed TDC and DCO, an all-digital phase-locked loop was designed in a top-down design flow. The design firstly started with automatic feedback control theory to complete Matlab mathematical modeling of ADPLL, then a suitable filter model according to the root locus diagram cloud be selected. Secondly completed the Verilog HDL design of digital filter and divider. Thirdly, to ensure the system is stable, the proposed PLL required a front-end system simulation based on VCS + HSIM simulation platform.Finally, the back-end design flow DC + ICC + Calibre was adopted to complete the layout design, and the post simulation results were given.The proposed ADPLL was designed in SMIC 180 nm CMOS process. The post simulation results showed a lock range of 640-to-1440 MHz with a 40 MHz reference frequency. The peak-to-peak and rms jitters were 35 ps and 4 ps, respectively. The PLL coreoccupies 0.053 mm2(0.244mm×0.218mm) and consumes 24.43 mW with a 1.8-V supply at1.44-GHz. The lock time is less than 2.4us. The simulation results, with respect to the recently proposed high-performance ADPLLs, show advantages of small area, low jitter, very high and wide output frequency.