Research Of A Model For An All Digital Phase-locked Loop Whose Control Parameter Modulus Can Be Automatically Generated

All digital Phase-locked loops(ADPLLs) have excellent performance and thus have become an indispensable component of modern circuits that are widely used in communications, electronics, measurement, computer and aerospace fields. Compared with analog PLLs, an all digital phase-locked loop(ADPLL) has more significant advantages. For example, it avoids the phenomenon of saturation by using analog components, also it eliminates the detrimental effects on system performance from direct-current drift by active filter and the phase detector, thus it owns higher reliability. In addition, it is easy for an ADPLL to be integrated in sopcs due to its digital structure. And with the development of high-speed VLSI technology, ADPLLs have become a focus of relative research feilds.The performance measures of ADPLLs include speed, frequency range and stability of phase lock, though they are represented in different structures. In traditional phase-locked loop, there exists a certain contradiction between the lock-in speed and stability. For avoiding the shortcomings of traditional ADPLLs such as difficult adjustment of circuit parameters, low lock-in speed and narrow lock-in range, anADPLL, which adopts an automatically controlled parameter named as modulus, is proposed. And thus an ADPLL with broad range of working frequncy occurs. The system is constructed by a digital phase detector based on dual D-type flip-flops, a loop filter from a reversible counter with variable modulo, a digitally controlled oscillator controlled by a pulse generation circuit, a controllable divider, two control modules respectively for phase and frequency. The phase control module automatically monitors the diffrence of input signals and output ones in real time, and through which the phase lock-in speed is promoted by changing the parameters of the loop filter. Likewise, the system stability is also ensured. The frequency detection module responds quickly to the frequency change of input signal, and controls the divider in real time. The lock-in phase range of the system is thus expanded.The design of the system is completed by using electronic design automation(EDA) technology, while simulation and analysis of the DPLL circuit are carried through computer aided technology, and finally, it is implemented on a FPGA hardware platform. System simulation and hardware test results verify that this system enables the digital filter and the parameters of the numerically controlled oscillator can be dynamically adjusted, in addition, the phase locking range is approximately within the frequency from 10 Hz to 50 MHz, and it arrives a stable lock-in state within two cycles of input signals, which means that the performance of the phase locked loop is improved observably. In a word, the proposed phase-locked loop is characteristic of its high lock-speed, wide lock range, simple circuit structure, flexible design of parameters, and easy integration in system level, etc., and also it can be applied to many different areas.