All Digital Phase-Locked Loop IP Core Research And Design

Phase-Locked Loop (PLL), which works as a clock synthesizer, has become a necessary and core part in modern SOC. It works on the top of the clock tree. Its performance directly influences and decides the highest frequency and stability of the whole chip. The higher the clock frequency is, the more PLL influences the performance of system. PLL technique has been one of the core techniques in modern SOC design.Modularization design and IP core reusing method make the VLSI (very large integrated circuit) design possible. PLL IP core has three types: pured anolog PLL,mixed-signal PLL and all digital PLL. Attaining continuous regulation of frequency, anolog PLL and mixed-signal PLL have very high precision. But they have some difficulities in designing this kind because the analog circuit must be achieved under digital techniques. ALL digital PLL has more advantages in some aspects. For example ,ADPLL is less difficulty to be designed, easier to be replanted in other technology, less locked-time and more tolerance with noise. So ADPLL becomes PLL designer's focus gradually.While the working frequency of PLL has reached 6GHz abroad, the frequency of domestic PLL with high-performance is still under 500MHz. So the PLL design technology becomes one of the bottlenecks for the design of domestic SOC. It is extremely urgent to have independent high-performance PLL with intellectual property. This article studies the relevant theories and key technology of all digital PLL with high performance and designs a new kind of programmable PLL. ADPLL has various design methods and most of them are nonlinear system. So there has none precise mathematics model describing ADPLL. In this paper, a precise mathematics model is described for our proposed ADPLL first. Subsequently, this system's stabilization is testified by autocontrol theory. At last, particular circuit design is introduced. The main content includes:1, It studies the mathematical models and working mechanisms of the all digital PLL (ADPLL) with high-performance. And also studies the steadily control theory of ADPLL. It creats a precise mathematical model for proposed ADPLL and tests its stabilization on Lyapunov theory.2, It studies the design technology of PLL under digital CMOS technics, and studies the implementation methods of the key part of PLL, especially the high-accuracy design technique of the digital-controlled oscillator and low dead-zone phase frequence detector. 3, It proposes a novel frequency acquisition mothod by separating frequency detecting from phase detecting process. It shortens the acquisition-time greatly.4, On the basis of the relevant theoretical research of PLL, this article designs a new kind of programmable PLL under the SMIC0. 13um CMOS technics. Simulations have shown that the ADPLL can work at more than 570MHz with low jitter.