The Research And Design Of A Novel Low-Noise Power Management System For RF Receiver

Recently, technology of communication, especially the wireless communication has developed greatly, which places high value on the technology of Radio Frequency(RF). Therefore, RF circuit has become the key part of communication, radar and microwave application system, and finds wide use in many fields. There are great challenges for RF ICs, the core parts of the RF communication products. Higher level integration has become the must solution of the RF ICs to achieve lower costs and better performances. Consequently, the integration of power management function into RF ICs is definitely and inevitably an important direction of the development of RF ICs.In this thesis, the research and design of the integrated low-noise power management for RF receiver chips, based on CMOS process, has been introduced. The source of power supply noise analysis is given. Based on this analysis, a power domain partition, targeting on suppressing the on-chip supply noise, is introduced. Different power supply block is applied for different circuit to alleviate the supply noise coupling. Combined the advantage of bandgap reference and the threshold voltage (VTH) voltage bias circuit, a ultra low noise voltage reference with digital calibration is designed. This voltage reference circuit can achieve both ultra low output noise and high accuracy. In addition, the on-chip LDO for both analog/RF and digital circuit has been designed.The circuits and layout of the proposed integrated low noise power management system for GPS RF receiver chip have been designed and post-simulated by SMIC0.18um CMOS technology. The proposed power management system has the advantage of ultra low noise, high reliability, high integration and digital controlled.