Low-jitter PLL for clock generator with supply-noise-insensitive VCO using DC-DC capacitive converter

Supply and substrate noise tend to cause the output clock of PLLs to jitter from their ideal timing. The design of low jitter PLLs has become a challenge because of the many design trade-offs between noise and bandwidth. In order to achieve a low jitter PLL design, fully differential signal and control paths to the voltage controlled oscillator (VCO) are maintained. Also, a proposed bandgap regulator using a capacitive charge pump for DC-DC converter (BRCC) helps to achieve a very high supply noise rejection capability. This proposed BRCC provides to reduce temperature sensitivities and to suppress low/high frequency power supply noise by a stacked cascoded N-type output transistors.; The analysis of the charge pump required boosting technique is derived from the calculation of rise time and boosted regulator output voltage. This stabilized architecture for the boosting technique in the high frequency supply noise (600mV/1ns) is described for providing adequate regulation for the stable clocking of the VCO in the charge pump. The simulated power supply noise rejection (PSNR) frequency response is at least -45dB for the VCO with BRCC.; Innovative circuits used in other blocks are designed with a great emphasis on reducing jitter. The loop optimizations of the PLL considering damping factor, bandwidth and noise are studied through behavioral transient simulation, tracking/capturing and jitter simulation with different power supply frequencies using CAD tools. The proposed behavioral modeling of the PLL using piecewise linear (PWL) model elements is presented as the top-down approach, which offers an exact estimation of high level PLL system behavior with a faster simulation time. The higher level of the PLL's closed loop behavioral modeling is developed to plot the PLL loop frequency response, optimize loop parameters and assure loop stability for all possible operating modes with PWL behavioral elements even in the continuous time domain.; The PLL design is fabricated in a 0.35um triple-metal digital CMOS process. The measured VCO dc power supply sensitivity is less than 20ps/V and the tuning range of the VCO is from 110MHz to 700MHz. When the PLL is running at 500MHz, the measured cycle-to-cycle jitter is less than +/-86ps (30ps rms) for a quiet 3.3V power supply. In the presence of 600mV peak-to-peak square noise signal of 20MHz at the power supply voltage, the cycle-to-cycle jitter is less than +/-161ps (42 ps rms). The power consumption of the PLL system is 42mW at 500MHz.