Research And Design Of A High Precision, Self-stable On-chip Low Drop-out Voltage Regulator

From the view of power management, this thesis begins with a deep investigation of Low Drop-Out voltage regulator's application and characterizations. Most LDO regulators before are off-chip so that they are hard to meet the demands of SOC solutions. This thesis is target on SOC applications and analyzes the challenges of stability, transient regulation and line regulation, etc. Trade-off relations between different characterizations are seriously discussed. In order to meet the demand of high precision and self-stability, a newly LDO structure is proposed and design process is carefully described, which manifest many design points.A PMOS is chosen to be the output transistor of this on-chip LDO. To maintain stability, miller capacitor in serious with nulling resistor is used. Miller capacitor is applied with two PMOS to reduce the dependence of metal capacitors, along with which PMOS capacitor testbench is developed.The breakthrough of this on-chip LDO design is to be able to provide large amount of current while keep very small drop-out voltage. Besides, quiescent, transient and frequency characterizations are needed to be maintained. Any process, voltage and temperature (P.V.T) variations should not compromise this LDO's regulation precision.This LDO is designed with the technology of SMIC 0.18um.