The Research On Self-Feedback Test For A Given Test Set

Nowadays,digital systems are widely used in our daily life.In order to guarantee the quality, carrying on a test to the integrated circuit (IC)is essential.With the rapid development of IC technique,IC is becoming more and more complex and the density of transistors increases dramatically, which make IC test much more difficult. Design-for-Testability(DFT) is a widely used method to solve the test problem.The fundamental idea of DFT, in order to make IC to be tested easily, is to consider the test issue while IC is designed.Build-In Self-Test(BIST) is a commonly used DFT technology. The Test Pattern Generator(TPG) and the Output Response Analyzer(ORA) are embedded in the circuit-under-test(CUT) in BIST scheme,so the CUT can be tested by itself. Recently, a new BIST scheme named Test Vectors applied by Circuit-under-Test(TVAC)is proposed.In this approach, CUT is not only regarded as test object, but also a sort of available resources.By choosing some of the interior nodes and connecting them to the primary inputs,as the first test vector is applied to the CUT, TVAC can generate and apply the next input vector by CUT itself. Compared with the traditional BIST, the main different phase of TVAC is test generation.TVAC has three strategies: Entire-Feedback, Group-Entire-Feedback and General-Feedback.For the Group-Entire-Feedback and General-Feedback, a grouping method named depth priority algorithm with information matrixes is presented, which can decrease the hardware cost of TVAC.The experimental results on ISCAS85 benchmark circuits demonstrate that the proposed algorithm can reduce average 19.35% hardware cost for Group-Entire-Feedback and 22.50% hardware cost for General-Feedback.On the basis of the grouping method, this thesis also proposes a feedback nodes assignment method for General-Feedback.This method can increase the fault coverage in a certain cycle's feedback. So it also can reduce the hardware to reach a given fault coverage for General-Feedback.The experimental results on ISCAS85 benchmark circuits demonstrate that the hardware cost can be reduced average 29.05% using the two proposed methods.Two TVAC structures for synchronous full scan sequential circuits are also presented in this thesis.The experiment is applied on ISCAS89 benchmark circuits with the proposed depth priority algorithm and feedback nodes assignment method for General-Feedback.The results show that, compared with the weighted random pattern test and Circular Self Test Path method,the TVAC scheme can reach higher fault coverage with smaller test vectors.