The Design Of An 8bit High-speed Track-and-hold

Optical communication systems demand medium-resolution analog-to-digital converters(ADCs)with thousands of MS/s.Due to the simpler structure and lower resolution of high-speed ADCs,its development is much faster than that of high-precision ADCs.In high-speed ADCs,multiple time-interleaving techniques are used widely.In order to reduce timing and bandwidth mismatch and improve overall ADC linearity,high-speed sample-and-hold is critical.In this thesis,an 8-bit resolution 2GS/s sample rate track-and-hold is designed for high-speed interleaved ADC front end used in optical communication systems.The main problem of conventional THA is hold-mode feed-through.In order to reduce the hold-mode feed-through,an open-loop double-switching track-and-hold architecture based on a cross-coupling capacitor technology is chosen.In the circuit module design,in order to improve the linearity of the input OTA,a double-switching differential OTA with source degenerated is used.In the main sampling structure,in order to increase the sampling rate and reduce the hold-mode feedthrough,a switching buffer with sampling capacitance structure is used.However,the MOS switch in the switching buffer structure will introduce clock feedthrough in the hold phase,therefore the clock-controlled coupling capacitors is applied to improve the clock feedthrough error.Using auxiliary feedback OTA to reduce hold pedestal,its structure and parameters are the same as the input OTA to make the two OTA match;Because of the clock signal is not the traditional square wave signal from the ground to the power supply,the traditional structure of clock buffer with latch can not reach the expected clock signal waveform.Therefore,in this paper,the design of the clock adopts the adaptive power supply/ground technology,which meets the requirement of a fixed high and low level clock signal.The schematic design and layout of the open-loop track-and-hold are fabricated in TSMC 40nm CMOS process,which occupies an area of 0.196mm~2.The post-simulation shows that the track-and-hold achieves a SNDR of 47.48dB,a SFDR of 47.55dB and a 7.59bit ENOB when operating at a sampling rate of 2GS/s and a sine-wave input signal with the frequency of 484MHz,the amplitude of±400mV.Moreover,the power consumption is 80.9mW.In general,the performance of the THA meets the design requirements.