Study And Design Of An Ultra High-speed Track/Hold Circuit

Analog to digital converter (ADC), as the key circuit of the signal conversion from analog to digital, is widely used in many fields such as modern communication, image acquisition,medical electronics and so on. With the development of software radio and high frequency communication, ADC is developing towards high speed, so the research on ultra high-speed ADC is widely concerned by academic circles.The track and hold circuit (THC) is an important part of the ultra high-speed analog to digital converter (ADC). Its role is to take instantaneous values of continuously varying analog input signals through the sample and hold into a discrete signal and maintain a period of time for the post core circuit quantization and coding. Because THC is located at the front end, its performance directly affects the entire ADC. How to ensure the accuracy of the situation, as far as possible to improve the sampling rate of THC is the key to the study.In this thesis, based on the background of the design of high-speed and high precision interpolation ADC, the open loop architecture is selected to design the ultra high-speed THC, and the key points of the speed and precision are studied according to the advantages and disadvantages of the open loop THC architecture; analysis of the effect of nonlinearity on the circuit performance, and by introducing the input buffer with source degeneration technique, high linearity bootstrapped switch and virtual switch charge injection absorption to improve the linearity of the circuit; two channel time interleaved architecture is adopted to improve the sampling rate of THC, and the manual calibration offset compensation technique is used to eliminate the errors of the two channels; the fully differential operational amplifier structure of full deep N-well structure is used as buffer; in addition, the power supply module is designed to supply power to the interstage buffer and the charge pump reset to reduce the acquisition time.In 1GSps sampling rate, using coherent sampling, the load capacitance is preamplifier parasitic capacitance, the input signal is 800mVpp sine wave, the simulation results show that the signal to noise and distortion ratio (SNDR) to 75.56dB, effective number(ENOB) of more than 12.25, reaching 12bits 1GSps ADC performance requirements for front-end THC.