Structure Design And Performance Analysis Of Nanometer SOI MOSFET

As the size of semiconductor devices into the nanometer regime according to the scaling-down rule, some device parameters have been approaching the inherent physical limits. All kinds of nanometer effects and reliability problems which limit the development of devices have become one of the challenges of the VLSI technology. One possible solution to these problems is to change the structure of the devices. The SOI MOS device has been regarded as a promising device in the nanometer regime and it is investigated in device structure, electrical characteristics and physical modeling for the novel SOI MOSFET in this thesis, respectively. The major research work and results are as follows:1. Based on the insulator halo, the dual-material-gate (DMG) MOSFET with the insulator halo is proposed. The process flow and the electrical characteristics for the novel device are presented, respectively. The results indicate that due to the unique step potential in the channel, the influence of the drain bias on the source is screened by the metal gate near the drain, thus improving the short-channel effects (SCE). Simultaneously, due to the second field peak, the transport efficiency of the electron increases so the drive currents. Besides, the field peak near the drain decreases which improves the hot-carrier-effect. The DMG structure coupling with the insulator halo, the threshold voltage roll-off and drain-induced-barrier-lowering (DIBL) decrease and the sub-threshold characteristics have been improved. Compared with the bulk MOSFET, the DMG MOSFET with the insulator halo has the higher transconductance and the lower inherent delay, and its cut-off frequency can achieve GHz. The offset between the on-state current (Ion),off-state current (Ioff) and SCE is implemented by adjusting the structure parameters.2. Based on the Poisson's equation, an analytical model of the threshold voltage for the DMG fully-depleted SOI MOSFET is proposed, considering the influence of the gate dielectric permittivity. The results show that the larger the gate dielectric permittivity is, the lower the minimum surface potential is, thus enhancing the capability of the gate to control the channel. Besides, when the gate length is fixed, with the ratio of the"control gate"length to the"screen gate"length increasing, the minimum surface potential has been decreasing. When the permittivity is between 3.9 and 20, the threshold voltage increases rapidly; when the permittivity is beyond 20, the threshold voltage tends to saturation.Further, the influence of the high-k gate dielectric on the DMG SOI MOSFET has been studied. An analytical subthreshold surface potential model for the DMG SOI MOSFET with high k gate dielectrics, which accounts for the short channel effect and the fringing field effect, has been developed. In this model, the new boundary conditions including the gate dielectric layer, the silicon layer and the buried oxide layer are given. Based on the surface potential, a 2-dimensional threshold voltage model with the short channel effect and the fringing field effect is deduced.3. An analytical subthreshold surface potential model for the DMG fully depleted SOI MOSFET with a single halo is presented. In this model, a single halo doping near the source in the channel and DMG have been considered to derive the channel potential using the explicit solution of the 2-D Poisson's equation. For simplity, a piecewise linear approximation method is proposed to deduce the surface potential profile. Based on the potential profile, together with the conventional drift-diffusion theory, the development of a subthreshold current model for the novel structure is deduced. Model verification is carried out using the 2-D device simulator ISE. Very good agreement is obtained between the model calculations and simulated results in the interesting region.4. Schr?dinger's equation is solved using an infinite rectangular well with a first-order perturbation and triangular potential well approximation, respectively. Then a compact drain current including the variation of barrier heights and carrier quantization in ultrathin-body and double-gate Schottky barrier MOSFETs (SBSD SOI MOSFET) is developed The carrier density thus obtained is included in the space charge density to obtain quantum carrier confinement effects in the modeling of thin-body devices. Due to the quantum effects, the first subband is higher than the conduction band edge. Thus the barrier heights at the source and drain increase and the carrier concentration reduces with the decreasing of drain current.Further, the influence of the high-k gate dielectric on the SBSD SOI MOSFET has been studied .With the dielectric constants increasing, the on-state currents degrade for SBSD SOI MOSFET. It is also shown that the influence of high-k dielectrics on the performance is quite different in the case that source/drain and gate electrode have an offset or overlap. For the source/drain and gate electrodes with an overlap, the structure with SiO2 interfacial layer between high-k gate dielectric and substrate is quite effective for increasing the drive current. For the source/drain and gate electrodes with an offset, the combination of high-k dielectric spacer with stack gate can significantly improve the on-state current. 5. The MOS capacitor with HfO2/SiO2/p-Si by ALCVD has been measured, which C-V curves show that the accumulation capacitances take on the frequency dispersion at high frequencies. Therefore, an equivalent five-element circuit model is proposed in the traditional two-frequency C-V correction. These extracted parameters by independently measuring the capacitor at two different frequencies eliminated the frequency dispersion at high frequencies. Due to the interface trap density, the C-V characteristics curve at high frequency has shown distortion. This thesis discusses the regulation of distortion about the high frequency MOS C-V characteristic curves and provides a data processing method, thus figuring out interface trap density distribution in the energy gap. Then, compared the ideal C-V curve with the experimental C-V curve, the electrical parameters of MOS capacitor are extracted, such as the shift of flat band voltage, the oxide trap density, the interface trap density at the SiO2/Si interface and the equivalent oxide thickness(EOT).In the conclusion, several novel SOI MOSFETs are proposed and studied on the device characteristics in this dissertation. The quantitative theoretical analyses are taken through numerical simulation and modeling methods to a great deal of basic mechanism problems. A lot of meaningful results are obtained and the guideline for the Nanometer SOI MOSFET is presented in this thesis.