Study Of Gate-Induced Drain Leakage And Gate Current In Gate-all-Around MOSFET

With the instruction of Moore's law,the short channel effect(SCEs)of traditional MOSFET has been even severe so that it can't longer meet the needs of industry.The nanowire gate-all-around(GAA)structure has been as one of the most promising candidates for future semiconductor device beyond 10 nm node,due to its unique gatewrap structure and superior gate control over channel.However,the GIDL leakage becomes more severe owing to the parasitic BJT in the channel and drain extension for GAAFET with the downscaling of device.Besides,the equivalent thickness of oxide becomes thinner,which leads to a greater gate current.As a result,increased leakage not only increases standby power consumption but also greatly affects device and circuit reliability and performance.In this thesis,the GIDL leakage and gate current were investigated to improve the static consumption for GAAFET by using Sentaurus TCAD.The major contents and achievements in this dissertation are as follows:Firstly,the GIDL effect performance on the main process parameters of GAAFET was simulated.The influence of structural parameter such as sidewall,underlap region,nanowire diameter,gate length and the doping gradient of source/drain extension region on GIDL dependence and device electrical characteristics were investigated systematically.According to the change of the longitudinal energy band below the channel surface 1 nm,the physical mechanism was revealed and analyzed.Compared with full Si O2 spacer GAAFET,the IOFF is 5 times lower and ION/IOFF is increased by 5 times in corner spacer(dual ? spacer)GAAFET.On this basis,a novel asymmetric insulated ring-on-channel GAAFET was proposed to greatly decrease the GIDL leakage and improve the device performance.The result indicates that compared to full vacuum spacer,its IOFF is reduced by 3 times and the ION/IOFF is increased by 3 times.In addition,based on the modeling of direct tunneling in MOS structure,the gate current dependence on key structure parameters and ambient temperature was simulated and analyzed to have a further understanding of the physical mechanism.Moreover,the effect of gate current on the basic logic cell inverter was also investigated.In a word,the work of this paper involved the major mechanism of leakage path in deep nanowire GAAFET,having important guiding significance on low-power device design and circuit reliability.