Research On Advanced MOS Devices In Nano-scaled Regime

Gate-all-around silicon nanowire transistors(SNWTs) with better gate control capability can be considered as one of the most promising structures to extend the device scaling down to the end of technology roadmap.In this work,the process integration technology of silicon nanowire has been studied to realize the self-aligned silicon nanowire on bulk substrate with large source drain fan-out.SNWTs with sub-10 nm diameter were successfully fabricated on bulk substrate with fully compatible CMOS technology by top-down approaches.Most of all,the advantage of the compatibility with conventional process can greatly decrease fabrication cost,simplify the whole process flow and have more feasibility.The drain-induced-barrier-lowering(DIBL) effect of 4 mV/V and subthreshold swing(S) of 74 mV/dec was obtained in the fabricated SNWTs with 5 nm gate oxide thickness and 130 nm gate length.Access to the high I_on/I_off ratio of 2×10⁸,which is highest I_on/I_off ratio of reported nanowire devices.