Study On Electrical Characteristics Of MOSFETs With High-κ Gate Dielectric

As Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is scaled down to below 32nm of feature length, improved performance-high speed, lower power consumption and decreased device volume - arises from the scaled capacitance of channel, voltage, and drain current as well as physical dimensions. In order to keep the higher driving force of semiconductor devices than before and smaller delay, an effective method that gives reduced gate thickness is taken out into practice. However, the reduced gate dielectric leads to increased gate-leakage current.Achieving these characteristics with low gate-leakage current requires that current SiO₂ dielectrics should be replaced with novel dielectrics with higher dielectric (high-κ) constant.Unfortunately majority of high-κmaterials are not work with silicon substrate and poly-silicon gate perfectly. The fundamental physics and material properties cause several undesirable reliability-gate leakage, thermal instability, electron traps- problems as well as the degradation of electrical performance. The relationships between some electrical characteristics, such as leakage current, C-V characteristics, Fringe induced barrier lowering (FIBL) and its electrical properties are discussed here.Theory analysis and software simulation have been done here to investigate the electrical performance of MOSFET with high-κgate dielectric. This paper introduces several gate leakage current mechanisms, such as direct tunneling (D-T), Fowler-Nordheim (F-N) tunneling, and hot-electron emission. ISE-TCAD 10.0 (Integrated Systems Engineering-Technology Computer Aided Design) has been used to simulate the gate leakage current, and the result indicate that F-N tunneling and hot-electron emission dominate the gate leakage current in high- dielectric, which is different from in traditional SiO₂ dielectric.The performance degradation in high-κMOS devices is mainly caused by interfacial traps between high-κdielectric and silicon channel and bulk traps inside high- materials, which has been verified. The effects of traps with different energies and types on capacitance-voltage (C-V) characteristics of MOS devices have been simulated and analyzed. The traps influence C-V characteristics in two aspects: increase the capacitance during traps capturing and releasing carriers; change the flat band voltage (VFB) of MOS device by capturing carriers. The application of high- gate dielectric increases the physical thickness, however, it leads much more obvious the effect of FIBL. The analysis has been done from electrical theory and ISE-TCAD simulation to investigate the FIBL mechanism and the effect of FIBL on threshold voltage (V_th) and Sub-threshold swing (S). This work analyzes the influence of source/drain shape on threshold voltage for the first time, conducting the design of the MOS device.