Performance Simulaton And New Device Structure Study Of Nanometer SOI MOSFET

With the shrinking size of the semiconductor devices, and the integration of circuits improved continuously, the short channel effects become more obvious, which have huge influence on the circuit performance, and limit the further miniaturization of the devices. To achieve better circuit performance, and overcome short-channel effects, measures have been taken from aspects of the material and structure of the semiconductor devices.Due to its'short channel effect(SCE) and lathc-up immunity, superior subthreshold characteristics, and low power consumption, SOI MOSFET has been regarded as one of the most promising device for 22nm node technology.To gain more excellent SCE performance and meet the require of VLSI design, many new SOI MOSFET structure have been developed. Dual material gate SOI MOSFET have two gates with different workfunctions. This introduces a potential step in the channel, and reduces the peak electric field at the drain end. Therefore, the structure achieves suppression of SCE. Channel engineering can also be used to improve the short-channel performance. By implanting high doping concentration impurities in the channel near source, the devices can circumvent short channel effects and drain induced barrier lowering efficiently.In the paper, research and analysis have been present on characteristics of small size devices, after brief introduction of SOI technology and fabrication. In the need of obtain more precise models for IC design, a new analytical model for dual material gate SOI MOSFETs with a single halo(DMGH) is derived, taking the 2-Deffects into consideration.Based on Poisson's equation and Laplace's equation, the potential distribution in both silicon film and buried layer is solved with boundary conditions. Considering the two-dimension effects in the buried layer,the front and back gate threshold voltage are derived respectively. The final threshold voltage of the device is the smaller one. The new model is verified with the two-dimensional device simulator Medici, and it shows better correlation with the numerical data. The simulation result indicates the dependence of threshold voltage on the thickness of the buried layer and other parameters. The short-channel immunity and DIBL suppression becomes better with decreasing thickness of the silicon film and the thickness of gate oxide.The development of small size SOI device structure is discussed in the fourth chapter, and the device performance and structure of the Multi-gate SOI MOSFET is introduced, which can achieve better control over the channel. Based on the impact of structural parameters on device characteristics, an ultra thin body SOI with thin buried layer and ground-plane back gate is present. The structure is defined with Medici, and the performance is analyzed. And mirroring the ground-plane doping, improvement can be obtained.In the conclusion, several novel SOI MOSFET are discussed in this dissertation. Quantitative theoretical analyses have been taken through numerical simulation and modeling methods in the hope of providing some guidelines for the Nanometer SOI devices under the technology node below 22nm.