Structure Design And Performance Analysis Of Novel Strained SGOI/SOI MOSFET

There has been a lot of interest in the strained-Si materials lately with its advantage of high-mobility, adjustable band structure and compatible technology with traditional silicon processing and wide application in the high-speed and high-performance devices and circuits.The SOI MOSFET device has been regarded as a promising device in the nanometer regime and it is investigated in device structure, electrical characteristics and physical modeling for the novel strained SGOI/SOI MOSFET in this thesis, respectively. The major research work and results are as follows:First, Based on the SOI structure, the strained-Si is used as the SOI MOSFETs’channel. A novel of fully depleted stack gate strained SGOI MOSFETs is developed. The process flow and the electrical characteristics for the novel device are presented, the band structure and other paramters of strained-Si model is shown. Also, based on the exact resultant solution of two dimension Poisson’s equation, a simple and accurate two-dimensional analytical model including surface channel potential, surface channel electric field threshold voltage and subthreshold swing for fully depleted stack gate strained SGOI MOSFETs have been developed. Investigated and expected to suppress the Short-Channel-Effects (SCE), the Drain-Induced-Barrier-Lowering (DIBL) and improve the subthreshold performance for nanoelectronics application. The two-dimensional analytical model predicts a shift, increasing potential barrier, in the surface potential, profile along the channel, which ensures a reduced threshold voltage roll-off and DIBL effects in this novel structure the subthreshold characteristic are greatly improved. The model is verified by numerical simulatior.These derived analytical models are in good agreement with the results of the two dimensional device simulatior ISE.A strained-Si fully depleted SOI MOSFET is presented, which has the advantages of strained-Si, high-k gate and SOI structure. A 2-D analytical model for the threshold voltage in strained-Si fully depleted SOI MOSFET with high-k dielectric is proposed by solving Possion’s equation. The model takes several important parameters into account. Relationships between threshold voltage, Ge profile and thickness of strained-Si are investigated. The result shows that the threshold voltage decreases with the increasing Ge profile and the strained-Si layer thickness. Relationships between threshold voltage, dielectric constant of high k gate and doping conceration of strained-Si layer are also investigated. The result shows that the threshold voltage increases with increasing dielectric constant of high-k and doping conceration of strained-Si layer. SCE and DIBL are analyzed, which also, it demonstrates that this novel device can suppress SCE and DIBL effect greatly.Secondly, based on the analysis the shortcoming of the traditional strained-Si MOSFETs and the advantage of double-gate MOSFETs, the double-gate strained-Si MOSFETs is presented. The process flow and the electrical characteristics for the novel device are presented. A novel of fully depleted symmetrical gate stack double gate strained-Si MOSFETs is developed. Based on the exact resultant solution of two dimensional Poisson’s equation, the novel two-dimensional models including surface potential, threshold voltage, subthreshold current and subthreshold swing, for gate stack symmetrical double-gate strained-Si MOSFETs have been developed. The model is verified by numerical simulation. Besides offering the physical insight into device physics, the model provides the basic designing guidance of further immunity of SCE of CMOS-based device in the nanoscale regime.In addition, a novel of asymmetric fully depleted double gate strained-Si MOSFETs is developed. The simple and accurate two-dimensional analytical models for new asymmetric double-gate fully depleted strained-Si MOSFET are developed. The models mainly include the analytical equations of the surface potential, surface electric field and threshold voltage, which are derived by solving two dimensional Poisson’s equation in strained-Si layer. The models are verified by numerical simulation. Besides offering the physical insight into device physics in the model, the new structure also provides the basic designing guidance for further immunity of SCE and DIBL of CMOS-based device in nanoscale scale.Thirdly, based on the analytical the advantage of dual-material gate (DMG) MOSFET, the thesis presents a novel DMG strained SGOI MOSFETs. A two-dimensional analytical model for the surface potential variation along the channel DMG strained SGOI MOSFETs. is developed. The analytical model takes into account the effects of different metal gate lengths, work functions, and the thickness of relaxed SiGe buffer. Also, it demonstrates that this novel device can suppress SCE and DIBL effect. The validity of two-dimensional analytical model is verified using numerical simulations.A novel DMG strained SOI MOSFETs is presented. A simple and accurate two-dimensional analytical model for the surface potential variation along the channel in fully DMG strained SOI MOSFETs is developed. We investigate the improved SCE, Hot Carrier Effect (HCE), the DIBL and carrier transport efficiency for the novel structure MOSFET. The analytical model takes into account the effects of different metal gate lengths, work functions, the drain bias and Ge mole fraction in relaxed SiGe buffer. The surface potential in the channel region exhibits a step potential, which can suppress SCE, HCE and DIBL. The strained-Si and SOI structure especially the strained-Si improves the carrier transport efficiency. The simple model for the threshold voltage can predicts a desirable "rollup" in the threshold voltage with decreasing channel length ratios L1/L2 and Ge mole fraction in relaxed SiGe buffer. The validity of two-dimensional analytical model is verified using numerical simulations.Furthermore, a fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is developed. On the basis of exact resultant solution of the two dimensional Poisson’s equations, a new accurate two-dimensional analytical model comprising surface channel potentials, surface channel electric field and the front and back channel’s threshold voltage for the fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs is developed. By comparing the the front and back channel’s threshold voltage, we get the threshold voltage of this novel MOSFET. Besides this device shows a good suppress SCE ability. The validity of the model is verifed useing the two-dimensional numerical simulator. Besides offering the physical insight into device physics, the model provides the basic designing guidance of fully depleted asymmetrical dual material gate double-gate strained-Si MOSFETs.In conclusion, several novel strained SOI MOSFETs are proposed and studied on the device characteristics in this thesis. The quantitative theoretical analyses are taken through numerical simulation and modeling methods to a great deal of basic mechanism problems. A lot of meaningful results are obtained and the guideline for the Nanometer SOI MOSFET is presented in this thesis.