Structure Study And Electrical Characteristic Analysis Of Novel SOI MOSFET

With the continuous development of semiconductor technology, the feature size of the metal-oxide-semiconductor field-effect transistor(MOSFET) is also continuously scaling down, and device structure and material is reaching to the psysical limitation. These influences of short channel effect and drain induced barrier lowering effect on threshold voltage is becoming more and more serious. The desirable solution is to change the structure of these devices and introduce new material to overcome the barrier.The novle device structure originated from combination of SOI、strained Si technology and the channel doping enginnering. The physical modeling has been proposed, analyzed and discussed further. The main research work and research results are as follows:1.In the paper, a single Halo fully depleted strain Si SOI MOSFET structure, which has the advantages of strained Si and Halo doping based on the SOI MOSFETstructure, has been proposed. Two-dimensional models are proposed by solving Poisson’s equation for the novle device. Theoretically, the characteristics have been analzed. The effect of Ge fractions in the relaxed layer on the built model parameters is investigated. Results show that the surface potential increases with the greater Ge fractions in the middle channel. howerer, the surface potential decreases with the greater Ge fractions near the source/drain end. The threshold voltage of the doping device is greater than the undoping device with the same Ge mole fractions; The threshold voltage is smaller with the greater strain values. The paper analyzes the impact of different drain voltages on the surface potential. The potential under Halo region is hardly influenced by the drain volage. The effect of Halo doping on threshold voltage and DIBL is investigated. The results show that the novel device can suppress the SCE and DIBL effect, and increase carrier transport speed.2. A novel symmetrical double-gate strained Si single Halo Metal-Oxide Semiconductor Field Effect Transistor with gate stack dielectric is proposed through the summary of deficiency of single-gate device and advantages of dual-gate device.The two-dimensional Poisson’s equation has been solved with suitable boundary condition by applying the parabolic potential approximation. This analytical model for the surface potential and the threshold voltage is derived. The strained Si channel is divided into two different doping regions, and the surface potential along the channel, compared with the normal double-gate device(uniform doping channel), exhibits a stepped potential variation, which can increase carrier transport speed. The impacts of drain-source voltage on short channel effects(SCEs) have been discussed; It’s shown that threshold voltage decreases with greater Ge mole fractions in butter layer, increases with the increase of the high-k layer dielectric permittivity of gate stack, and increases with the greater doping concentrations in the channel near the source, which are analyzed and explained its physical mechanism; Results show that the novel device can suppress threshold voltage roll-off and SCEs, which provides the basic designing guidance for the CMOS-based devices in nanometer scale.3. A novel double-gate(DG) strained Si MOSFETs(metal-oxide-semiconductor field-effect transistors) in which the top and bottom gates consist of three laterally contacting material with different work functions is proposed in this paper. The two-dimensional(2D) analytical models for the surface potential, surface electric field and threshold voltage are presented. The effects of Ge fractions X on the model parameters are investigated. The effect of the ratio of triple-material length on threshold voltage and drain induced barrier lowering is discussed. The characteristics of the device are studied as compared with the single-material(SM) double-gate MOSFETs. The results show that the structure can increase the carrier transport speed and suppress the drain induced barrier lowering(DIBL) effect. Different length ratios of three-material gate have been optimized to minimize short-channel effects(SCE) and drain induced barrier lowering effects.4. A dual material gate strained Si SOI MOSFET structure with asymmetric Halo,which has the advantages of strained Si, channel doping engineering and DMG structure, has been proposed. Two materials with different work function are put together to form the gate. Considering both the characteristics of the new device structure and the influence of strain, the flatband voltage and built-in potential have been corrected.The two-dimensional analytical models for the surface potential,et al, are proposed by solving Poisson’s equation for the novle device. The effect of Ge fractions in the relaxed layer on surface potential and threshold voltage is investigated. Results show that the surface potential shows two potential steps distrition and surface electric field yields two peak electric field,which increase greatly carrier transport speed. The novle device can suppress the SCE and DIBL effect, which has a certain significance to the theoretical study. In conclusion, a few novel device structures are proposed and studied.The physical model is set up accurately and analyzed thoroughly. Hence, we obtain a great deal of meaningful results, which presents the beneficial guideline for the nanometer MOSFET in the thesis.