Simulation And Experimental Study On MOSFET With High-k Gate Dielectric

With the continuous development of semiconductor technology, the feature size ofthe metal-oxide-semiconductor field-effect transistor （MOSFET） is also continuouslyscaling down. However, gate leakage current and static power consumption increasedramatically due to quantum tunneling effect as the thickness of conventional SiO₂gatedielectric is reduced to the level of several atomic layers. To overcome these problems,the use of the high dielectric constant （high-k） gate dielectric to replace SiO₂hasbecome an inevitable trend. However, when the physical thickness of the high-k gatedielectric becomes comparable to the channel length of the device, influence of thefringing-induced barrier lowering （FIBL） effect on the threshold voltage becomes moreand more serious besides short-channel effect （SCE） and drain-induced barrier lowering（DIBL） effect. Aiming at the above problems, theoretical and experiment workinvolving the characteristics of MOSFET with high-k gate dielectric and preparation ofhigh-k gate dielectric materials is respectively performed to find relevant solutions inthis thesis. Theoretically, the influences of high-k gate dielectric on the characteristics ofMOSFET are studied, and threshold voltage model is established by considering theseparasitic effects. Experimentally, atomic layer deposition （ALD） technology is used todeposit high-k gate dielectric materials, and the physical and electrical properties ofthese materials are analyzed in detail.The characteristics of nano-scale MOSFET with high-k gate dielectric areinvestigated. With the aggressive reduction of feature size of MOSFET, some physicalphenomena （such as: gate leakage current, SCE, etc.） continuously occur to weaken theperformance of MOSFET. Meanwhile, the use of high-k gate dielectric introduces anfringing-induced barrier lowering （FIBL） effect, which can greatly degrade the off-statecharacteristics of MOSFET. An equivalent coupling capacitance theory is presented tohelp understanding the FIBL effect, and can explain the physical mechanism behind theFIBL effect better. By optimizing the device structure （adopting low-k sidewallmaterials, shorter sidewall length, lower junction depth and shorter gate/LDDoverlapped region length, etc.）, the FIBL effect can be well suppressed, and the off-satecharacteristics are improved. The FIBL effect can also be suppressed by using stackedgate structure, especially, when the underlying material using a low-k material. Similarto other studies on the FIBL effect, off-state leakage current is used to characterize theeffects of FIBL. However, in some special cases, there are some phenomenona which are difficult to explain by this method. Thus, a new research method of off-state leakagecurrent is presented. The total leakage current is divided into three parts: source leakagecurrent, substrate leakage current and gate leakage current. The influences of FIBLeffect and DIBL effect on each component are investigated respectively. The resultsshow that, for the practical application of nano-scale MOSFET with high-k gatedielectric, the source leakage current becomes a major component of the total leakagecurrent. The proposed method can help studying and understanding the off-statecharacteristics of nano-scale MOSFET with high-k gate dielectric.Ultimately, the changes in the off-state leakage current of high-k MOSFET arecaused by threshold voltage fluctuations. So, it is particularly important to study thethreshold voltage behavior of high-k MOSFET. The study investigates the influence ofthe voltage drop across the lightly-doped-drain （LDD） region and the built-in potentialon MOSFET, a threshold voltage model for high-k gate dielectric MOSFET isdeveloped by solving the2D Poisson’s equation. The model can predict the FIBL effectand the SCE. Based on this model, the relationship between the threshold voltageroll-off and the channel length, drain voltage and the gate dielectric permittivity isinvestigated. Compared with the non-LDD MOSFET, the LDD MOSFET depends thechannel length, the drain voltage and gate dielectric permittivity lightly. Meanwhile, inorder to solve the problem of poly-silicon gate depletion, the introduction of metal gateneeds to establish a new threshold voltage model for high-k/metal gate MOSFET. Thestudy investigates the influences of the metal-gate and high-k/SiO₂/Si stacked structureon MOSFET. The flat-band voltage is revised by considering the influences of stackedstructure and metal-semiconductor work function fluctuation. A threshold voltageanalytical model for metal-gate/high-k/SiO₂/Si stacked MOSFET is developed bysolving these Poisson’s equations using the boundary conditions. These two models areverified by numerical simulation, the results show that the theoretical model calculationresults and simulation results are in good agreement.Experimentally, in order to improve the thermal stability of HfO₂gate dielectric,HfAlO thin film is deposited using atomic layer deposition （ALD） technology byalternating the growth of HfO₂and Al₂O₃. The physical characteristics and electricalproperties of the HfAlO film deposited on p-type （100） Si substrates are investigated.The growth principle of HfAlO using TMA+H₂O and TEMAH+H₂O is analyzed. Theformation of Al-O-Hf-O （Hf-O-Al-O） bond in the film is revealed to impact thecharacteristics of Hf-Al-O films. And the properties of the deposited film vary with thechanges in the proportion of Hf and Al. With the number of cycles pulsed of Al₂O₃and HfO₂in one bilayer, the influences of Al-O-Hf-O （Hf-O-Al-O） unit on thecharacteristics of the Hf-Al-O film are gradually weakened. The behavior of depositedfilm gradually becomes similar to that of a simple stack of HfO₂and Al₂O₃. In additionto H₂O, O₃is also used as the oxidant to deposite the HfAlO gate dielectric film. It canbe seen from the analysis results, there are no differences in the composition andbonding manner of the HfAlO thin film prepared by the O₃and the H₂O as oxidantrespectively. Due to the strong oxidizing nature of the O₃, an obvious shift of C-V curveis observed and a low dielectric constant interfacial layer is formed, leading to a smalldielectric constant of deposited HfAlO gate dielectric film. However, the annealingprocess can improve the electrical characteristics.