Research Of Scan Design Techniques For The Low Test Power Under Area Constraint

With the process technology advancing, the complexity of integrated circuits(ICs) is increasing dramatically. This makes a great challenge for the testing of ICs. Design-for-testability(Df T) technique can facilitate the testing of ICs and it has been adopted in IC design. As an efficient Df T technique, scan design has been most widely applied. However, it has been shown that a large number of transitions will be caused during the testing by scan design, which will result in great test power consumption in the circuit under test(CUT). Excessive power consumption during test application may result in circuit damage, increased product cost, decreased system reliability and overall yield. Test power has become a major concern in Df T technique. How to reduce the test power caused by scan design has become an important issue to be considered during the IC design process.It was shown that the transitions caused by the shifting of test data contribute most to the test power consumption. Reduction of transitions plays an important role in the optimization of test power. Scan chain modification is an effective method to reduce the number of transitions during test application. In this work, we propose an improved test power optimization method by inserting extra logic in scan chain. It explores suitable places in scan chain based on an accurate criterion to insert different linear functions so as to minimize the transitions caused by shifting test data through scan chain. The different linear functions consist of XOR gates and inverters. The connection cost of each two scan cells with different linear functions inserted is evaluated and compared to determine which linear function is most beneficial to the optimization of test power. The experimental results show that number of transitions caused by the scan design by the proposed method can be reduced by 10.93% averagely while 2% area overhead is incurred. This method is more efficient to reduce test power than other optimization methods by inserting extra logic while incurring low area.However, scan chain modification with inserting extra logic incurs some area overhead. Scan chain modification by introducing blocking logic provides a better tradeoff between test power and area overhead. Such blocking logic can freeze all transitions during test data shifting into the CUT while introducing some hardware overhead. Thus, how to implement the blocking logic with minimum area cost deserves more research effort. In this work, a method based on blocking logic by transmission gate is proposed to realize the test power optimization. Also, to control the area overhead due to the blocking logic, transmission gates will be inserted on the output of some selected scan cells. For other scan cells, two complementary connection styles can be selected to achieve further reduction of transitions without any area overhead introduced. The combination of two optimization methods enables the scan design to satisfy the constraint on area while minimizing the transitions during test application. The experimental results show that the average reduction of transitions of the proposed method has been reduced to 41.80% when 2% area overhead is incurred. The optimization effect of proposed method is better than other similar methods based on blocking logic.As a whole, this work proposed two optimization methods based on scan chain modification. They can successfully overcome the weaknesses of other existing methods and achieve better performance of test power while incurring acceptably low area overhead. The proposed methods can not only be applied on the single scan chain design but also on the multiple scan chain design. Future work will focus on the relation between test power and the structure of CUT, which guides a new angle to optimize test power during test application.