Design And Implementation Of Low Power Scan Test In Power Line Communication Asic

With the rising of complexity and integration of digital integrated circuit, thenumber of transistors per unit area and test vectors is rising dramatically. This causedhigher test frequency and longer testing time, highlighted the problem of high testpower consumption. The impact from test power are mainly reflected in three aspects.First, excessive power dissipation during test leads to increased temperature in theCUT, making the use of expensive packages for the removal of excessive heatimperative. Second, high power dissipation leads to high current density which is themajor factor determine electromigration rate. Because electromigration causes theerosion of conductors and subsequently leads to circuit failure, high test powerdissipation severely decrease CUT reliability. Third, excessive peak power will leadto serious IR drop and noise. These may decrease yield.Aiming at the problem of high test power, we analyze the principle of scan testand power consumption, and present an approach for reducing the power consumedduring scan testing. The key of the approach is decreasing the overall switchingactivity. So we introduce the weighted transitions metric (WTM) which is stronglycorrelated to the switching activity during scan-in and scan-out operations. Theproposed approach which is based on the greedy algorithm can reorder scan cell forminimizing WTM efficiently. In order to reduce the hardware cost and performanceloss, the position information of scan cell in the chip physical layout is considered too.The proposed approach completed the PLC chip design from netlist to final GDS,successfully applied in low test power design. Compared to the result which is notoptimized, the average power consumption and peak power consumption during scantesting are reduced by20.3%and15%. Testing time, test coverage and chip area areno change, only routing length increased by6%. The results show that the approachcan reduce the test power consumption effectively without changing the cost of chip.The significance of this paper is integrating the approach into the physical designflows, forming a new process of low-power scan test design. The new flow can solvethe problem of high test power effectively. This article makes low-power scan testfrom theory research to the actual project design, has very important practicalapplication value.