Research And Design On Pipeline Analog-to-Digital Converter

With the rapid growth of wireless communication systems and portable video device, such as wireless LAN in communication, cell phone and high-resolution digital TV in custom electronic products,the demand for low-power and high-speed integrated circuits is indispensable.In all of ADC (analog-to-digital convertor, referred to as ADC or A/D convertor) architectures,pipeline architecture has to be the most efficient for achieving a good high input frequency dynamic performance and a high throughput.This paper aimed to improve the sampling rate and designed a 12 bit 200Msps pipelined analog-to-digitalconverter in deep submicron TSMC 0.18μm CMOS technology. Research and innovation are as follows:(1)The thesis put forward a new CCII-based doubling sample-and-hold circuit. Breaking the traditional sample-hold-sample mode,the DSH circuit achieves a reasonable use of time and achieves the two modes of sample-hold-sample and keep hold-sample-hold at the same time, achieving 200Msps sampling rate.Through PSPICE simulations show that the circuit has good performance.(2) The thesis put forward a new multiplying digital to analog converter (multiplying digital to analog convertor,referred to as MDAC) circuits based on CCII,achieving doublely sampling rate and the difference of magnification.a good realization of the MDAC function, while the sampling rate also reached a 200Msps. Through PSPICE simulations show that MDAC circuit with high performance.Based on pipeline ADC,the main content of this works includes as follow.(1)The 10-stage,1.5bit/stage and 2 bit flash ADC last stage structure is introduced.And digital correction circuits are added to diminish errors between stages.(2) The whole circuit consists of the doubling sample-and-hold circuit, the Sub-ADC,the Sub-DAC,the clock generator, the time synchronizer and the digital calibration circuit.(3)The ADC circuits are controled by a single clock.The clock is using the clock tree to reduce the load on the circuit and using double edge flip-flop to achieve delay circuit(4) Decoder circuit make use of decoding method based on current mode logic gate circuit:the thermometer code are converted into binary code which further improve the conversion speed of decoder and reduces the ADC's error rate.Besides,the paper does simulation to the pipeline ADC.Simulation results show that the measured static INL and DNL errors of the 12 bit ADC are 0.95LSB and 1.01LSB respectively with a 5MHz input is 200Msps,and disspates 165mW power consumption at the power voltage is 1.8V.