| Frequency synthesizer is the core device of RF front-end in wireless communication.In the field of wireless com munication,a high-precision reference frequency is necessary.The modulation and demodulation of wireless signals must rely on the reference frequency signal.The phase-locked loop(PLL)frequency synthesizer adopts the phase-locked loop method to realize frequency synthesis.It has the advantages of wide operating frequency band,low phase noise,low power consumption and easy integration.It is currently the most commonly used frequency synthesis technique.Among them,the fractional frequency division method can make the PLL have a higher loop bandwidth while using a higher reference frequency,so it is widely used.Although the fractional PLL achieves high frequency resolution,it also brings the problem of fractional spurs.This paper mainly studies the fractional divider circuit applied in the high performance RF frequency synthesizer system,adopts the sigma-delta modulation method to realize the fractional frequency division,and focuses on the problem of the fractional spur suppression.Mainly completed the following research:This paper expounds the basic principle and common structure of the fractional frequency divider based on sigma-delta modulation.The fractional frequency divider based on sigma-delta modulation is mainly divided into two modules:sigma-delta modulator and high-speed frequency divider.The key parameters of the fractional divider such as phase noise,fractional spurs and sources of frequency resolution are derived and analyzed in detail.This paper uses 0.13 μm SiGe BiCMOS process to design the high-speed frequency divider and sigma-delta modulator circuit respectively.First of all,this paper studies the high-speed frequency division technology,and designs a trigger unit based on source-level coupling logic,so that the high-speed frequency divider can continuously divide the frequency in the ku frequency band.Its maximum operating frequency can reach 16 GHz,and the maximum frequency division ratio can reach 219-1.Then this paper studies the high-precision and programmable ∑-Δ modulation technology,and designs a 32-bit high precision ∑-Δ modulator.The order of the modulator is programmable between 1～4 orders,and the modulo of the modulator can be programmed between 1～232-1,which greatly improves the frequency accuracy of fractional frequency division.This design extends its use to frequency synthesis systems that require rational precision.Finally,the source of the fractional spur and the periodicity of the output sequence are analyzed.By studying the spurious suppression technology,an improved fractional spurious suppression method is proposed,which combines the prime modulus value and the addition of jitter,and finally realizes the optimization of the sigma-delta modulation technique.In this paper,the layout of the fractional divider is designed and simulation is done.After simulation verification,the fractional frequency divider based on ∑-Δ modulation designed in this paper can continuously divide the frequency in the frequency range of 7～16GHz,the frequency division ratio can reach 219-1,the power supply voltage is 3.3V,and the power consumption is 46.14mA.The frequency resolution is as high as 0.047Hz,and the fractional spur is lower than-62.79dBc.These indicators reach the advanced level of similar products. |
