Research And Design Of 40GHz Frequency Dividers For Ultra-Wideband Millimeter-Wave Frequency Source

In recent years,with the demand for high-quality,large-data-capacity communications and the advent of the5G era,the communication technologies applied to the Ku,K and Ka bands have become hot topics in the industry.In the RF transceiver system,a Phase Locked Loop(PLL)frequency synthesizer is one of the most critical modules.It provides the transceiver with a precise frequency,high stability local oscillation signal,and its performance has direct influence to the entire wireless network.Divider is one of the most important sub-modules of PLL and the design is difficult.Therefore,it is of great significance to design a frequency divider with low power consumption,high speed,and programmable frequency output.Based on 130nm SiGe BiCMOS process,this paper designs a high-speed divide-by-two divider with operating frequencie of 24~40GHz and an 8/9 dual-mode prescaler with operating frequency of 12~20GHz.The divide-by-two divider uses the combination of flip-flops and logic gate structure with wide operating frequency and high sensitivity and the flip-flops use current mode logic(CML)structure.Circuit parameters are designed by optimizing the self-resonant frequency and other methods.The 8/9 prescaler uses synchronous 4/5 divider for the first stage and asynchronous divide-by-two divider for the second stage.An optimal 8/9 dual-modulus divider logic circuit is obtained through digital circuit logic analysis,which can guarantee a short delay and improve the working speed of the divider.In order to further improve the operating speed of the flip-flop,it also uses the embedded logic gate technology,the master-slave flip-flop asymmetric technology,the output voltage swing optimization technology and the split load technology.The 4/5 divider and the asynchronous divide-by-two divider are connected by an emitter follower-type buffer which has strong driving ability.The output uses a three-stage self-biased inverter buffer to drive the load.The layouts of the high-speed divide-by-two divider and8/9 prescaler are given respectively.The key points in the divider layout design are discussed in terms of placement and routing.The post-simulation results of the high-speed divide-by-two show that:in the tt process corner,-55~125°C,3.3V power supply,the input clock signal 0dBm conditions,the operating frequency range of15~46GHz;in the 24 to 40 GHz input frequency range,the phase noise is lower than-125.78dBc/Hz@1kHz and-147.42 dBc/Hz@1MHz;the average operating current is less than 4.0mA and the chip area is 490×440?m~2.Extract the key signal lines and longer traces of the 8/9 dual-mode divider for electromagnetic field simulation,and the other circuits perform post-simulation,the results of the circuit electric field hybrid simulation show that:in the tt process corner,-55~125°C,3.3V power supply,the input clock signal 0dBm conditions,the operating frequency range is 15~46GHz;in the input frequency range of 24~40GHz,the phase noise is lower than-125.78dBc/Hz@1kHz and-147.42 dBc/Hz@1MHz;the average operating current is lower than 4.0mA,and the chip area is 490×440?m~2,which meet the target requirements.Above all,the high-speed divide-by-two divider and the 8/9 prescaler designed in this paper can be applied to the“Ultra-wideband millimeter wave frequency source”project.With slight adjustment,they can also be applied to other millimeter wave frequency synthesizers.