Drfm Gaas Ultra-high-speed Adc, Dac Circuit Design And Implementation,

Digital radio-frequency memory (DRFM), which is based on high-speed sampling and digital storage, can save and reconstruct the radio or microwave signal. So, it has become an effective method to interfere modern radar and has been developed into an essential part of modern electronic countermeasure (ECM). The most important parameter is instantaneous bandwidth (IBW) which is detemiined by the bandwidth of high-speed ADC and DAC. But unfortunately, high resolution, high-speed, wide bandwidth ADC and DAC are very difficult to be realized, that counteract the utilization of DRFM. The main target of this work is to design and realize the high-speed GaAs 3bit phase digitizing ADC and DAC for 3bit phase DRFM, including many research fields such as the GaAs process flow, device modeling, circuit design, characterization and test of circuits, etc.The detailed steps of device modeling are discussed and an improved Genetic Algorithm is proposed for the extraction of GaAs MESFET small signal model. This algorithm which is implemented by Matlab is successfully used to determine the small-signal equivalent circuit of GaAs MESFET from the measured S parameters in the range of 0.1 GHz to 1 OGHz and can fit measured S parameters very well. The results can be extrapolated well up to 20GHz. The impact of different sidegating bar material and different orientation on the sidegating threshold voltage is discussed. And the light-induced sidegating effect is also analyzed. The research results provide a reliable reference for making layout designing rules of large scale GaAs MESFET digital IC.A modified process flow that is fit for the large scale GaAs IC is designed based on the existing process condition of Nanjing Electronic Devices Institute's (NEDI's) GaAs 0.5um standard full ion-implanted process. By many process experiments, the best nonuniformity of threshold voltage has been obtained so far. Also the better layout of MESFET and diode is designed according to the demanding of GaAs high-speed ADC, DAC. So, the layout design rule can be established based on the above results and many problems in the circuit layout are discussed. Monte Carlo methods are used to analyze the yields and performance of GaAs FLASH ADCs. That discusses the objective of process control monitor for the ADC from the theoretical analysis.Design, realization, and test of a monolithic GaAs 3bit phase digitizing DAC is detailedly described. The 0.5um fully ion-implanted GaAs MESFET is used to fabricatethe circuit in NEDI. Also detailedly analyzes the characterization of phase digitizing DAC's static and dynamic performance. Such parameters as time nonlinear parameters (TDNL, TINL), amplitude nonlinear parameters (ADNL, AINL) and phase nonlinear parameter (PNL) can be used to describe its static performance. Such parameters as spurious-free dynamic range (SFDR), near range harmonic distortion (THD6), effective work bandwidth (EWB), output signal power and coherency of two orthogonal output signal can be used to describe its dynamic performance. Test results show that its static performance is excellent. Its EWB is more than ].5GHz, and phase accuracy is better than 4%. Its SFDR is better than 16 dBc.This paper detailedly describes the design, realization and test process of 3bit phase GaAs ADC. The ADC is implemented by NEDI's GaAs 0.5um non-self-aligned standard full ion-implanted process and D-mode MESFETs. The characterization and test method of phase digitizing ADC is also discussed. Phase nonlinear parameters (PDNL, PINL) are used to describe the static performance. IBW and phase accuracy depending on the frequency can be used to describe the dynamic performance. Test results indicate PDNL< ±0.01 LSB, PINL< ±0.007LSB. The ADC can operate at 2GHz sampling rate with 1.2Gbps output code rate and its IBW is nearly 150MHz with the phase accuracy of ±0.22LSB.At last, Design, realization and test of a high-speed GaAs monolithic 4bit DAC and 3bit ADC are discussed. The circuits have all been fabricated in NEDI's GaAs 0.5um non-self-aligned standard full ion-implanted process. Its DNL is ±0.22LSB, and 1NL is ±0.45LSB. The accuracy of this 4bit DAC is up to 5.2bit. The highest code conversion rate of the 4bit DAC is 2Gbps, and its settle time is less than 250ps. The power dissipation of the core circuit is 11 OmW. The test results of 3bit ADC show that its function is right. But its LSB output can't be tested because layout mistake. It can be predicted that using above design method and circuit topology, the good test results can be obtained after correcting the layout mistake.