The Research On DFT Structure And Test Scheduling Optinization For Hierarchical SOC

With the development of design methodology and the advancement of manufacturetechnology, the scale of IC (Integrated Circuit) grows larger and larger, thus the Soc(System on chip) appears. In order to ensure the reliability and shorten the designcycle of the product, the IP (Intelligence property) reuse technology is widely used inthe design of Soc. However, more and more small-scale SOCs are instantiated as newIP core to realize more and more complex function, which causes the multi-layerembedded structure of Soc, thus bringing great complexities for the test ofhierarchical SOC. How to simplify the test of hierarchical SOC and reduce test timebecomes an urgent problem to be solved.Currently, designers usually improve the testing efficiency from two aspects:hardware and software. Hardware method mainly refers to the design of testarchitecture, which includes test wrapper cell, test access mechanism (TAM) and soon. Software method mainly refers to the development of test scheduling strategy.Many domestic and international scholars have made great numbers of research onSoc DFT, most of the study is focused on the flattening Soc. However, the study inDFT methods of hierarchical Soc is seldom published. Based on this situation, thisthesis carries out related research on test architecture and test scheduling strategy ofthe hierarchical Soc.This thesis proposes two different DFT plans of hierarchical SOC which is differedby whether each IP core is seen as a whole in the test. According to these plans, twodifferent testability architectures and test scheduling optimization strategies aredeveloped and verified on the ITC’02, the standard international benchmark circuitsrespectively. Furthermore, in order to illustrate the practicality of these DFT plans, theEPON-MAC SOC designed by our team is selected as the platform to verify relatedalgorithms. The Experimental results demonstrate that both two proposed DFT plansof hierarchical Soc can effectively reduce the test time.The main contents and research results of this thesis are listed as follows:1.A DFT plan of hierarchical Soc based on dual-level collaborative optimization isproposed, in which each IP core of hierarchical Soc is seen as an entire module. It ismainly used to solve the problem that traditional test scheduling strategy only makesoptimization on the top layer of SOC. Both DFT architecture and test schedulingstrategy optimizations are implemented to shorten the test time of hierarchical Soc. 2.For the above DFT plan, the corresponding DFT structure is designed.Furthermore, the wrapper cell which can test parent cores and child cores in parallelas well as the connection and glue logic among cores is proposed. Moreover, the keyschematics including TAM structures and test control units of TAM are designed forthis wrapper unit.3.Based on the above DFT architecture, the optimized test scheduling algorithm isestablished. The algorithm which works on both the top layer and sub-cores of Socmakes use of the packing theory to simplify the test scheduling problem ofhierarchical Soc. It ensure the shortest test time for entire hierarchical Soc and alsomake the test time for each individual IP cores as less as possible under the conditionof limited testing resources which usually means to TAM width. The verificationresults on the ITC’02platform demonstrate that the method proposed in this thesis ismuch more efficient than any other existing methods.4.A DFT plan of hierarchical Soc based on Virtual Flattened scan chain is proposed.It is can ensure hierarchical Soc maintaining the original structure in normal mode,while the ISC from different IP cores to a virtual layer in test mode. This plan canovercomes the defect of low utilization of test resources caused by the situation thatthe length of a certain or several internal scan chains in core is significantly longerthan others.5.For the above test plan, a DFT architecture is design and relevant algorithm modelis established. The optimization based on Virtual Flattened scan chain breaks the scanchains from different IP cores in different layer of Soc and then reconfigure new scanchains in a virtual layer. The equalization for these new scan chains can minimize thetest time of hierarchical Soc in test mode while maintaining the original structure innormal mode. Experimental results indicate that this method make a further reductionon the test time of hierarchical Soc. Unfortunately, however, when using this method,the original test pattern of each IP core should be regenerated which increases thefollow-up work volume.