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1. Research On Key Techniques Of NoC-based Many-Core Testing
2. Research On Low Cost Deterministic Built-in Self Test (BIST)
3. Research On Optimization Techniques For SOC Test Time
4. Research On Design For Test Methodology For Core Based SOC Architecture
5. A Fast And Low Power Consuming DFT Design Method Based On Scan Array
6. The Research On Noc Communication Architecture Test Methods
7. The Research On Optimizing The Test Time On Three-dimensional Integrated Circuits
8. Surrogate Data And Its Application
9. Intel Nor Flash Class Testing Process Optimization And Realization
10. The Research Of Sensor IC QUIBS Test Cost Reduction
11. Time Parameter And Dc Parameter Measurement Unit For IC Test System
12. Research On Built-in-self-test Of Memory-blocks In FPGAs Based On Minimizing Configurations
13. Research Of Scan Tree Design For The Reduction Of Test Time And Test Power
14. DFT Analysis And Optimization In PLC Chip
15. The Research On NoC Communication Architecture Test And Ip Cores Test Scheduling Methods
16. The Research On Automated Penetration Testing Technology Merged Petri Net
17. Research And Implemetation ORFS Test Optimization
18. Research On Optimization Techniques For SoC Test Scheduling
19. A Study On ATE And Bench Test Cost Reduction
20. Research And Analysis Of Design For Testability Based On PCIE IP Core
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