Research On Electrostatic Protection Based On Advanced IC Technology

In the current IC industry,especially chip products with more advanced technology,the hidden danger of product failure caused by Electrostatic Discharge(ESD)is getting higher and higher,and ESD failure has become the main factor leading to chip reliability problems.The phenomenon of static electricity can be seen everywhere in daily life,and the IC industry has taken measures in all aspects from the source to the application of the final product for the protection of static electricity.With the transformation of IC manufacturing process,the design difficulty of on-chip ESD protection is also increasing.In this thesis,the design of ESD protection under advanced IC process,including ESD devices and all-chip circuits,will be studied and summarized in detail.The main contents are as follows:(1)Several common ESD protection devices under 40 nm CMOS process are studied,mainly focusing on the principle of the device and TLP test characteristics,including PN junction diode series,MOSFET series and SCR series.By adjusting the PN junction area and changing the width of the device,the robustness of the device in discharging ESD current is improved.The improvement of MOSFET device infrastructure is studied,and the working principle of MOSFET device is explored through the test results.In addition,the influence of GGNMOS device layout rendering mode is also explored.The basic structure of SCR and the working mechanism of devices such as MLSCR and LVTSCR based on the improvement of SCR structure are studied.Combined with TLP test results,the optimization method of trigger voltage and sustain voltage of MLSCR device is introduced.(2)Based on the on-chip ESD protection content,the full-chip ESD protection network structure of a module in the 40 nm chip is introduced in detail.Combining the BCM parameters under the 40 nm process,it focuses on the extraction of the design window of the chip module port,and then introduces the ESD full chip protection scheme used by the module.The power protection unit RC Power Clamp under 40 nm process is also studied,including equivalent circuit,device structure and layout drawing.And according to the ESD protection plan made,TLP test is carried out on the chip die after the tape out.Organize and analyze the test results,and provide the TLP test results of various modes(PS,NS,PD,ND)under the full-chip ESD protection network of the module port.(3)When the IC system is impacted by a fast ESD event(such as CDM),the ESD protection device should have the ability to quickly turn on the conduction current at this time,otherwise it will increase the risk of ESD.MDTSCR has a current gain amplifier module embedded in the traditional DTSCR,which makes the parasitic bipolar junction transistor's current gain much higher than that of the traditional DTSCR,making the trigger voltage smaller and speed up the turn-on speed of the device.By adjusting the number of diode strings in the device trigger module,MDTSCR can adapt to different ESD design windows.Experimental results show that compared with traditional DTSCR devices,the turn-on time of MDTSCR under 28 nm CMOS process is reduced by 52%,and the trigger voltage is reduced from 5.5V to 4.5V.